SLAAEI9A December   2023  – May 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1305 , MSPM0L1306 , MSPM0L1345

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM8 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad
    2. 2.2 Migration Process
      1. 2.2.1 Step 1: Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3. Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4: Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash and EEPROM Features
      2. 3.2.2 Flash and EEPROM Organization
        1. 3.2.2.1 Flash and EEPROM Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power UP and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of MSPM0
        2. 3.6.1.2 Interrupt Controller (ITC) of STM8
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Mode Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Interintegrated Circuit Interface (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

3.5.1 Operating Modes Comparison

Table 3-9 gives a brief comparison between STM8 and MSPM0 devices.

Table 3-9 Operating Modes Comparison Between STM8 and MSPM0 Devices
STM8 MSPM0
Operation Mode Description Operation Mode Description
Run mode CPU and peripherals run normally after a system or power reset. RUN 0 MCLK and CPUCLK run from a fast clock source (SYSOSC)
Low power run mode CPU and peripherals run with a low speed oscillator (LSI or LSE). All interrupts must be masked. 1 MCLK and CPUCLK run from LFCLK (at 32kHz).
2
Wait mode CPU operation stops. Oscillator remains enable. Selected peripherals keep running. Wait mode is entered from Run mode by executing a WFI or WFE instruction. SLEEP 0 CPU operation stops. SYSOSC remains enable. LFOSC remains enable. MCLK run from a fast clock source (SYSOSC).
1 CPU operation stops. SYSOSC remains enable. LFOSC remains enable. MCLK run from LFCLK.
Low power wait mode CPU operation stops. Low speed oscillator remains enable. Selected peripherals keep running. This mode is entered when executing a Wait for event in low power run mode. All interrupts must be masked. 2 CPU operation stops. SYSOSC remains disable. LFOSC remains enable. MCLK run from LFCLK.
Active-halt mode(STM8S) CPU operation stops. Oscillators are disable except LSI or HSE. Almost all the peripherals are stopped except AWU. the MVR regulator is powered on. STOP(2) 0 CPU operation stops. Status of SYSOSC is retained(1). LFOSC remains enable. ULPCLK is limited to 4MHz. PD0 is enabled and PD1 is disabled. And analog peripherals such as ADC can operate.
1 Same as STOP0, with the SYSOSC and ULPCLK gear shifted to 4MHz.
Active-halt mode with MVR auto power off(STM8S) CPU operation stops. Oscillators are disable except LSI only. Almost all the peripherals are stopped except AWU. the MVR regulator is powered off. 2 CPU operation stops. SYSOSC is disabled. ULPCLK runs at 32kHz. PD0 is enabled and PD1 is disabled.
Active-halt mode (not STM8S families) CPU operation stops. Oscillators are disable except LSI or LSE. Almost all the peripherals are stopped except RTC, AWU, and so forth. The voltage regulator is at low power mode. STANDBY 0 CPU operation stops. SYSOSC is disable. All PD0 peripherals receive the ULPCLK and LFCLK.
Halt mode CPU operation stops. Oscillators are disable(3). Almost all the peripherals are stopped. The voltage regulator is at low power mode(3). 1 Similar to STANDBY0, with only TIMG0/1 receiving ULPCLK or LFCLK.
N/A N/A SHUTDOWN No clocks are available and device is shut down.
(1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), then SYSOSC remains enabled as in RUN1. If STOP0 is entered from RUN2 (SYSOSC disabled and MCLK sourced from LFCLK), then SYSOSC remains disabled as in RUN2.
(2) MSPM0C devices don't have the STOP1 mode.
(3) LSI oscillators of STM8L001xx and STM8L101xx devices are enabled on halt mode if IWDG is activated and no watchdog in Halt option is disabled. Only BEEP and IWDG keep running on halt mode if activated and no watchdog in Halt option disabled.

STM8L05xx devices have five low power modes: Wait mode, Low power run mode, Low power wait mode, Active-halt mode and Halt mode. STM8L001xx and STM8L101xx devices have three low power modes: Wait mode, Active-halt mode and Halt mode. STM8 series have four low power modes: Wait mode, Active-halt mode, Active-halt with MVR auto power off, and Halt mode.