SLAAEI9A December 2023 – May 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1305 , MSPM0L1306 , MSPM0L1345
The MSPM0 family is based on the ARM Cortex M0+ CPU core architecture. The STM8 family is based on the STM8 CPU core architecture. Table 3-1 gives an overview of the general features of the CPU in the MSPM0 family compared to the STM8.
| Features | STM8L and STM8S | MSPM0C, MSPM0L and MSPM0H |
|---|---|---|
| Architecture | Enhanced STM8 CPU core | Arm Cortex M0+ |
| Data bus width | 8-bit | 32-bit |
| Instruction set | Complex Instruction Set | Reduced Instruction Set |
| Number of instructions | 80 | 56 |
| Multiplication instruction | MUL (8 by 8) | MULS (32 by 32) |
| Division instruction | DIV (16 by 8), DIVW (16 by 16) | MATHACL supports 32-bit division(1) |
| Pipeline | 3-stage | 2-stage |
| Operating Freq (Max) | 16MHz or 24MHz(2) | 24MHz or 32MHz(3) |
| DMA | Yes | Yes |
| Coremark/MHz | unavailable(4) | 2.39(5) |