SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

3.2.2 Simulation Results With Ansys® HFSS

The following simulation results evaluate the impact of anti-pad size on return loss and impedance continuity in the design example:

  • Figure 3-2: Simulation model for landing pad and anti-pad structure.
  • Figure 3-3: Return loss (S11) simulation result with different anti-pad size.
  • Figure 3-4: TDR impedance simulation result with different anti-pad size.

Key observations:

  • Without anti-pad (red curve), the impedance deviation is maximized and the return loss (S11) is significantly degraded.
  • Different anti-pad size results in different impedance change and return loss (S11) performance.
  • In this design example, an anti-pad size 1.4 × wider than the landing pad achieves the best return loss (S11) performance.
Simulation Model for Landing Pad and Anti-Pad Figure 3-2 Simulation Model for Landing Pad and Anti-Pad
Return Loss (S11) With Different Anti-Pad Size Figure 3-3 Return Loss (S11) With Different Anti-Pad Size
TDR Impedance With Different Anti-Pad Size Figure 3-4 TDR Impedance With Different Anti-Pad Size

Key recommendations for AC coupling capacitor landing pad:

  • Use anti-pad under the components when the landing pad size is larger than the matched 50Ω high-speed trace width (for example, IC pins, AC coupling capacitors, ESD diodes, line fault resisters).
  • The size of the anti-pad depends on the specific PCB stackup, the recommendation is to perform a high-speed simulation to determine the proper anti-pad size.
  • If possible, select a PCB stackup where the high-speed trace width matches the largest component pad size (for example, 0402 pad size). This approach helps to eliminate the need of anti-pads under the components and has the best impedance continuity.