ESD diode inherent parasitic capacitance can significantly degrade signal integrity in high-speed applications. For instance, a 0.2pF parasitic capacitance impacts return loss (S11) at 6.75GHz as in the following:

1. Equation 3 details the capacitive reactance calculation.
   Equation 3. ${\mathrm{Z}}_{\mathrm{c}}=\frac{1}{\mathrm{j}\mathrm{w}\mathrm{C}}=-\mathrm{j}\frac{1}{2\mathrm{\pi }\mathrm{f}\mathrm{C}}=-\mathrm{j}\frac{1}{2\mathrm{\pi }\times 6.75\mathrm{G}\mathrm{H}\mathrm{z}\times 0.2\mathrm{p}\mathrm{F}}=-118\mathrm{j}\mathrm{\Omega }$
2. Equation 4 shows the parallel impedance with 50Ω transmission line.
   Equation 4. ${\mathrm{Z}}_{\mathrm{p}\mathrm{a}\mathrm{r}\mathrm{a}\mathrm{l}\mathrm{l}\mathrm{e}\mathrm{l}}=\frac{50\times (-118\mathrm{j})}{50-118\mathrm{j}}$
3. Equation 5 is the return loss degradation.
   Equation 5. $\mathrm{Return\; loss\; (dB)}=20{\log }_{10}|\frac{{\mathrm{Z}}_{\mathrm{parallel}}-50}{{\mathrm{Z}}_{\mathrm{parallel}}+50}|=-13.7\mathrm{dB}$

Assuming the original return loss is –30dB at 6.75GHz (typical for high-speed interfaces), the degradation caused by the 0.2pF capacitance is approximately 16.3dB.

As Figure 3-16 shows, the return loss (S11) across the entire PCB channel worsens progressively as ESD diode capacitance increases.

Parasitic capacitance from ESD diode inherent capacitance and ESD diode landing pad both severely impact impedance and return loss performance. Therefore, compensating for this capacitance effect is necessary.

• Using an anti-pad under the ESD diode can be a viable option to compensate for the parasitic capacitance.
• If anti-pad is not enough to compensate the capacitance:
  • Create anti-pad on more layers to make the signal trace refer to a deeper ground layer. For instance, create anti-pad on layer 2 and layer 3, and let the signal refer to layer 4. This increases dielectric thickness, raising more impedance to counteract capacitance effects.
  • Slightly narrow the trace near the ESD diode to compensate the capacitance. The narrowed trace introduces higher inductance, transforming the original parasitic capacitance into an inductor-capacitor-inductor (L-C-L) T-coil model, which can effectively compensate the capacitance-induced impedance drops.

Figure 3-17 is an example of slightly narrowing the trace near the ESD diode and enlarging the anti-pad to compensate parasitic capacitance effects.

Figure 3-18 compares the entire PCB channel return loss (S11) between the narrowed trace design and the original trace design (with ESD diode parasitic capacitance = 0.2pF). After optimization, the entire PCB channel (from the IC pin to the connecter via) return loss is improved by 3dB at 6.75GHz, and 4dB at 5.4GHz.

Key recommendations for the ESD diode:

• Reduce the ESD diode capacitance value to a lowest possible value (≤ 0.2pF). Increased parasitic capacitance degrades both return loss and insertion loss performance.
• Use compensation techniques in PCB layout design, such as adding single layer or multilayer ground cut-out (anti-pad) under the ESD diode, or narrowing the trace width near the ESD diode to compensate for the capacitance impact.
• Place the ESD diode directly onto the high-speed trace to avoid any stub.
• Place the ESD diode by use case. For systems requiring short-to-battery testing, the ESD diode can be placed on the chip-side of the AC coupling capacitor. For systems that are not requiring short-to-battery testing, the ESD diode can be placed as close as possible to the connector side for better ESD performance and signal integrity.
• Performing simulation to validate compensation strategies is highly recommended.