SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

3.3.3.1 Simulation Results (Non-Functional Pad Impact)

This section provides the simulation results of the non-functional pad impact:

  • Figure 3-10: Pad-stack structure with and without NFPs in the middle layers
  • Figure 3-11: Return loss (S11) with and without NFPs
  • Figure 3-12: TDR impedance simulation result with and without NFPs

NFPs can severely influence return loss performance, the developer recommends removing the non-functional pads on unconnected layers.

Pad-Stack Structure With and Without NFPs Figure 3-10 Pad-Stack Structure With and Without NFPs
Return Loss (S11) Comparison With and Without NFPs Figure 3-11 Return Loss (S11) Comparison With and Without NFPs
TDR Impedance Comparison With and Without NFPs Figure 3-12 TDR Impedance Comparison With and Without NFPs

Key recommendations for through-hole connector footprint:

  • The developer strongly recommends simulating the connector footprint based on board stackup.
  • Connector signal via anti-pad size is the dominant factor for impedance control; therefore, requiring meticulous consideration in the design.
  • Add surrounding ground vias, the ground vias spacing can also affect impedance and needs to be taken into account.
  • Remove the NFPs on unused layers.
  • Follow the footprint recommendations of the connector vendor.