SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

Abstract

In automotive applications, high-speed signal interfaces such as video serializer/deserializer (SerDes), Multi-Gigabit Ethernet, USB3.x, and DisplayPort (DP) are increasingly deployed to meet growing bandwidth demand. The single-link data rate of these interfaces can reach multi-gigabit or even tens of gigabits per second.

Signal integrity (SI) is critical for reliable high-speed signal transmission, as waveform distortions caused by reflections, impedance mismatches, crosstalk, or signal attenuation can lead to data corruption and communication failures. To provide robustness, these interfaces define stringent S-parameter requirements, including return loss (S11) and insertion loss (S21), across the entire high-speed channel to maintain maximum performance.

For instance, TI's latest FPD-Link SerDes can now support data rates up to 13.5Gbps over a single coax cable to support 4K+ resolution display. The total FPD-Link™ interface channel comprises a printed circuit board (PCB), passive components, connectors, and cables. Among these, PCB layout design plays a pivotal role in signal integrity preservation. Key design considerations include controlled trace impedance, strategic component placement and via placement, anti-pad sizing, parasitic capacitance mitigation, and so forth.

This application note takes the FPD-Link coax channel design as an example, focusing on PCB channel design requirements and actionable layout design guidelines to optimize PCB S-parameters.