SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)

This section provides the simulation results of the surrounding ground vias impact:

  • Figure 3-8: Return loss (S11) with different ground via spacing
  • Figure 3-9: TDR impedance simulation result with different ground vias spacing
Return Loss (S11) With Different Ground Vias Spacing Figure 3-8 Return Loss (S11) With Different Ground Vias Spacing
TDR Impedance With Different Ground Vias Spacing Figure 3-9 TDR Impedance With Different Ground Vias Spacing

The simulation results from Figure 3-6 to Figure 3-9 demonstrate that anti-pad size is the dominant factor for connector signal via impedance control due to the direct impact on capacitance; however, ground vias spacing is also important for managing impedance and cannot be neglected.