SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

3.1 Transmission Line Impedance Impact

Figure 3-1 shows the transmission line model used in the design example. The impedance of a PCB transmission line is determined by the interplay of trace width, trace thickness, substrate height, trace-to-copper clearance, PCB dielectric constant (Dk), and coating above the trace.

  • Trace width: A wider trace increases the capacitive coupling between the signal trace and the reference plane, which lowers the impedance.
  • Trace thickness: A thicker trace increases capacitive coupling to the reference plane, this lowers the impedance slightly.
  • Substrate height: A thinner dielectric layer (smaller distance between the signal trace and reference plane) increases the capacitive coupling, this lowers the impedance.
  • Trace-to-copper clearance (ground strip separation): Narrower clearance from the trace to adjacent copper increases fringe capacitance coupling to neighboring copper. This reduces impedance by increasing parasitic capacitance.
  • PCB dielectric constant (Dk): A higher dielectric constant increases the capacitance between the trace and reference plane, thereby lowering the impedance.
  • Solder mask and solder coating: The solder mask and solder coating adds a dielectric layer over the signal trace. This increases the effective dielectric constant (Dk) near the trace and lowers the impedance.

To main a consistent 50Ω transmission line impedance:

  • Make sure of a uniform trace width and spacing throughout the signal path.
  • In PCB manufacturing, etched copper traces have distortions and irregular rectangular cross-sections due to the inherent etching factor. The resulting profile is trapezoidal. In this design example, the upper trace width is 5.3mil, while the lower width is 6.3mil. Align these geometric dimensions with the process capability of the PCB fabricator.
Transmission Line Model For Impedance Calculation Figure 3-1 Transmission Line Model For Impedance Calculation

Key recommendations for transmission line impedance:

  • Use an impedance calculator to determine maximum impedance parameters
  • Close trace-to-copper spacing can reduce the impedance by 2Ω–3Ω, consider the effects of the spacing
  • Solder mask on the trace can reduce the impedance by 2Ω to 3Ω, consider the effects of the solder mask
  • Maintain impedance control of fabricated the PCB within 50Ω ±5%