SLAAET6 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1S-Parameter Definition
    1. 1.1 Insertion Loss (S21)
    2. 1.2 Return Loss (S11)
  5. 2High-Speed Signal Design Example Of FPD-Link™ Serializer Body
    1. 2.1 Design Example Overview
    2. 2.2 Key Points in High-Speed FPD-Link Layout Design
  6. 3Factors Impacting Return Loss and Optimization Guidelines
    1. 3.1 Transmission Line Impedance Impact
    2. 3.2 AC Coupling Capacitor Landing Pad Impact And Optimization
      1. 3.2.1 Mitigation Strategy: Anti-Pad Implementation
      2. 3.2.2 Simulation Results With Ansys® HFSS
    3. 3.3 Through-Hole Connector Footprint Impact and Optimization
      1. 3.3.1 Through-Hole Connector Via Anti-Pad Impact
        1. 3.3.1.1 Simulation Results With Ansys® HFSS
      2. 3.3.2 Surrounding Ground Vias Impact
        1. 3.3.2.1 Simulation Results (Surrounding Ground Vias Impact)
      3. 3.3.3 Non-Functional Pad Impact
        1. 3.3.3.1 Simulation Results (Non-Functional Pad Impact)
    4. 3.4 Generic Signal Via Impact and Optimization
      1. 3.4.1 Simulation Results
    5. 3.5 ESD Diode Parasitic Capacitance Impact and Optimization
  7. 4Summary

2.2 Key Points in High-Speed FPD-Link Layout Design

In high-speed signal design, proper PCB layout is required to achieve maximum signal integrity. General guidelines focus on managing signal reflection, attenuation, and crosstalk.

  • Reflection control:
    • Caused by impedance discontinuities (for example, vias, connectors, trace width change)
    • Signal reflections degrade return loss (S11)
    • Need to maintain a consistent 50Ω single-ended impedance across the entire signal path
  • Attenuation control:
    • Caused by conductor resistance and dielectric losses in PCB substrates
    • Attenuation reduces signal amplitude and edge sharpness, which degrades insertion loss (S21)
    • Use low-loss dielectric PCB materials or reduce trace length to minimize attenuation
  • Crosstalk control:
    • Caused by electromagnetic coupling between adjacent signal traces
    • Crosstalk induces noises, timing jitter, and logic errors
    • Increase spacing between high-speed traces, and add ground shielding to minimize crosstalk

Since reflection control is the most challenging aspect, critical factors and design variables are analyzed and optimized to achieve better reflection through simulation in this application note. This helps the designer address return loss degradation caused by capacitor landing pad, ESD diode parasitic capacitance, signal via, and through-hole connector. Optimization key points are highlighted in the following list:

  • Transmission line impedance control:
    • Maintain 50Ω single-ended trace routing with impedance control of ±5%
    • Make sure the reference plane is complete above or below the high-speed trace
    • Route the high-speed trace as a microstrip on the top layer or bottom layer to avoid any stubs
  • Impedance control at the component level in the following list:
    • AC coupling capacitor landing pad
    • ESD diode landing pad and inherent parasitic capacitance
    • Through-hole connector footprint
  • Impedance control at the through-hole signal vias:
    • Minimize signal via numbers, eliminate via stubs
    • Optimize signal via anti-pad and add ground transition vias to minimize impedance discontinuity

In summary, the key principles for high-speed SerDes routing is well-controlled impedance. This requires maintaining a uniform 50Ω impedance profile across the entire signal path, even when traces change layers through vias or pass through ESD diodes or capacitors.

The following section analyzes all these optimization key points in detail. Design models, simulation results of return loss and Time-Domain Reflectometry (TDR) impedance, actionable layout design recommendations are provided for optimizing PCB S-parameters.