SLASFB6 December   2025 MSPM33C321A

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
      12.      23
      13.      24
      14.      25
      15.      26
      16.      27
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
      4. 7.5.4 VBAT current consumption
    6. 7.6  Flash Memory Characteristics
    7. 7.7  Power Supply Sequencing
      1. 7.7.1 Power Supply Ramp
      2. 7.7.2 POR and BOR
      3. 7.7.3 VBat Characteristics
      4. 7.7.4 Timing Characteristics
    8. 7.8  Clock Specifications
      1. 7.8.1 System Oscillator (SYSOSC)
      2. 7.8.2 High Frequency Crystal/Clock
      3. 7.8.3 System Phase Lock Loop (SYSPLL)
      4. 7.8.4 Low Frequency Oscillator (LFOSC)
      5. 7.8.5 Low Frequency Crystal/Clock
    9. 7.9  Analog Specifications
      1. 7.9.1 ADC Specifications
        1. 7.9.1.1 ADC Electrical Characteristics
        2. 7.9.1.2 ADC Switching Characteristics
        3. 7.9.1.3 ADC Linearity Parameters
        4. 7.9.1.4 Typical Connection Diagram
      2. 7.9.2 COMP Specifications
        1. 7.9.2.1 Comparator Electrical Characteristics
        2. 7.9.2.2 COMP DAC Electrical Characteristics
      3. 7.9.3 VREF Specifications
        1. 7.9.3.1 VREF Voltage Characteristics
        2. 7.9.3.2 VREF Electrical Characteristics
      4. 7.9.4 Analog VBOOST Specification
        1. 7.9.4.1 Analog Mux VBOOST
      5. 7.9.5 Temperature Sensor
    10. 7.10 Serial Interface Specifications
      1. 7.10.1 UART
        1. 7.10.1.1 UART
      2. 7.10.2 I2C
        1. 7.10.2.1 I2C Characteristics
        2. 7.10.2.2 I2C Filter
        3. 7.10.2.3 I2C Timing Diagram
      3. 7.10.3 SPI
        1. 7.10.3.1 SPI
        2. 7.10.3.2 SPI Timing Diagram
      4. 7.10.4 CAN
        1. 7.10.4.1 CAN
      5. 7.10.5 QSPI
        1. 7.10.5.1 QSPI
        2. 7.10.5.2 QSPI Timing Diagram
      6. 7.10.6 I2S/TDM
        1. 7.10.6.1 Serial Audio
        2. 7.10.6.2 I2S/TDM Timing Diagram
    11. 7.11 Digital IO
    12. 7.12 TRNG
      1. 7.12.1 TRNG Electrical Characteristics
      2. 7.12.2 TRNG Switching Characteristics
    13. 7.13 Emulation and Debug
      1. 7.13.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Arm Cortex-M33 core with TrustZone and FPU
    2. 8.2  Power Management and Clock Unit (PMCU)
      1. 8.2.1 Power Management Unit (PMU)
      2. 8.2.2 Clock Module (CKM)
      3. 8.2.3 Operating Modes
        1. 8.2.3.1 Functionality by Operating Mode
    3. 8.3  Device Memory Map
      1. 8.3.1 Memory Organization
      2. 8.3.2 Peripheral Memory Map
    4. 8.4  NVIC Interrupt Map
    5. 8.5  Embedded Flash Memory
    6. 8.6  Embedded SRAM
    7. 8.7  DMA
    8. 8.8  Event Manager
    9. 8.9  Error Aggregator Module (EAM)
    10. 8.10 GPIO
    11. 8.11 IOMUX
      1. 8.11.1 Input/Output Diagrams
    12. 8.12 Analog Modules
      1. 8.12.1 HSADC
      2. 8.12.2 COMP
      3. 8.12.3 Temperature Sensor
      4. 8.12.4 VREF
      5. 8.12.5 Device Analog Connections
    13. 8.13 Security and Cryptography
      1. 8.13.1 Global Security Controller (GSC)
      2. 8.13.2 AESADV
      3. 8.13.3 SHA256
      4. 8.13.4 Public Key Algorithm (PKA)
      5. 8.13.5 TRNG
      6. 8.13.6 Keystore
      7. 8.13.7 CRC
    14. 8.14 Serial Communication Interfaces
      1. 8.14.1 UNICOMM (UART/I2C/SPI)
        1. 8.14.1.1 UART (UNICOMM)
        2. 8.14.1.2 I2C (UNICOMM)
        3. 8.14.1.3 SPI (UNICOMM)
      2. 8.14.2 CAN-FD
      3. 8.14.3 Quad SPI (QSPI)
      4. 8.14.4 Digital Audio Interface - I2S/TDM
    15. 8.15 LFSS
    16. 8.16 Timers, RTC and Watchdogs
      1. 8.16.1 Timers (TIMx)
      2. 8.16.2 RTC_A
      3. 8.16.3 IWDT
      4. 8.16.4 WWDT
    17. 8.17 Serial Wire Debug Interface
    18. 8.18 Bootstrap Loader (BSL)
    19. 8.19 Device Factory Constants
    20. 8.20 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.16.1 Timers (TIMx)

The timer peripherals in these devices support the following key features, for specific configuration see Table 8-18:

Specific features for the general-purpose timer (TIMGx) include:

  • 16-bit and 32-bit timers with up, down or up-down counting modes, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Two independent CC channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode
  • Shadow CC register available in TIMG4_n (n = 0, 1, 2, 3) and TIMG12_0
  • Shadow load register available in TIMG4_n (n = 0, 1, 2, 3) and TIMG12_0
  • Support quadrature encoder interface (QEI) for positioning and movement sensing available in TIMG8_n (n = 0, 1)
  • Support synchronization and cross trigger among different timer instances in the same power domain
  • Support interrupt/DMA trigger generation and cross peripherals trigger capability
  • Cross trigger event logic for Hall sensor inputs TIMG8_n (n = 0, 1)

Specific features for the advanced timer (TIMA0_x) include:

  • 16-bit timer with up, down or up-down counting modes, with repeat-reload mode
  • Selectable and configurable clock source
  • 8-bit programmable prescaler to divide the counter clock frequency
  • Repeat counter to generate an interrupt or event only after a given number of cycles of the counter
  • Up to four independent CC channels for
    • Output compare
    • Input capture
    • PWM output
    • One-shot mode

  • Internal 5th and 6th internal CC channel for capture/compare events

  • Shadow register for load and CC register available in both TIMA0_0 and TIMA0_1
  • Complementary output PWM
  • Asymmetric PWM with programmable dead band insertion
  • Fault handling mechanism to ensure the output signals in a safe user-defined state when a fault condition is encountered
  • Support synchronization and cross trigger among different TIMx instances in the same power domain
  • Support interrupt and DMA trigger generation and cross peripherals (such as ADC) trigger capability
  • Two additional capture/compare channels for internal events
Table 8-18 TIMx Configurations
TIMER NAMEPOWER DOMAINRESOLUTIONPRESCALERREPEAT COUNTERCAPTURE / COMPARE CHANNELSPHASE LOADSHADOW LOADSHADOW CCDEADBANDFAULTQEI
TIMA0_0 PD1 16-bit 8-bit 8-bit 4 + 2 Yes Yes Yes Yes Yes –
TIMA0_1 PD1 16-bit 8-bit 8-bit 4 + 2 Yes Yes Yes Yes Yes –
TIMG4_0 PD1 16-bit 8-bit – 2 –

Yes

Yes

 – – –
TIMG4_1 PD1 16-bit 8-bit – 2 –

Yes

Yes

 – – –
TIMG4_2PD116-bit8-bit–2–

Yes

Yes

–––
TIMG4_3PD116-bit8-bit–2–YesYes–––
TIMG8_0 PD0 16-bit 8-bit – 2 – – – – – Yes
TIMG8_1 PD0 16-bit 8-bit – 2 – – – – – Yes
TIMG12_0PD132-bit––2––Yes–––
Table 8-19 TIMx Cross Trigger Map (PD1)
TSEL.ETSEL Selection TIMA0_0, TIMA0_1 TIMG8_0, TIMG8_1 TIMG4_2, TIMG4_3 TIMG12_0
0 TIMA0_0.TRIGO Reserved Reserved Reserved
1 TIMA0_1.TRIGO Reserved Reserved Reserved
2 TIMG4_2.TRIGO TIMG4_2.TRIGO TIMG4_2.TRIGO TIMG4_2.TRIGO
3 TIMG4_3.TRIGO TIMG4_3.TRIGO TIMG4_3.TRIGO TIMG4_3.TRIGO
4 TIMG12_0.TRIGO TIMG12_0.TRIGO TIMG12_0.TRIGO TIMG12_0.TRIGO
5 TIMG8_0.TRIGO TIMG8_0.TRIGO TIMG8_0.TRIGO TIMG8_0.TRIGO
6 TIMG8_1.TRIGO TIMG8_1.TRIGO TIMG8_1.TRIGO TIMG8_1.TRIGO
7 to 31 Reserved
18-31 Reserved
Table 8-20 TIMx Cross Trigger Map (PD0)
TSEL.ETSEL SelectionTIMG4_0TIMG4_1
0TIMG4_0.TRIG0TIMG4_0.TRIG0
1TIMG4_1.TRIG0TIMG4_1.TRIG0
2 to 31Reserved

For more details, see the TIMx chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference Manual.