SLASFH8 March   2026 MSPM33C321A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
      12.      23
      13.      24
      14.      25
      15.      26
      16.      27
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
      4. 7.5.4 VBAT current consumption
    6. 7.6  Flash Memory Characteristics
    7. 7.7  Power Supply Sequencing
      1. 7.7.1 Power Supply Ramp
      2. 7.7.2 POR and BOR
      3. 7.7.3 VBat Characteristics
      4. 7.7.4 Timing Characteristics
    8. 7.8  Clock Specifications
      1. 7.8.1 System Oscillator (SYSOSC)
      2. 7.8.2 High Frequency Crystal/Clock
      3. 7.8.3 System Phase Lock Loop (SYSPLL)
      4. 7.8.4 Low Frequency Oscillator (LFOSC)
      5. 7.8.5 Low Frequency Crystal/Clock
    9. 7.9  Analog Specifications
      1. 7.9.1 ADC Specifications
        1. 7.9.1.1 ADC Electrical Characteristics
        2. 7.9.1.2 ADC Switching Characteristics
        3. 7.9.1.3 ADC Linearity Parameters
        4. 7.9.1.4 Typical Connection Diagram
      2. 7.9.2 COMP Specifications
        1. 7.9.2.1 Comparator Electrical Characteristics
        2. 7.9.2.2 COMP DAC Electrical Characteristics
      3. 7.9.3 VREF Specifications
        1. 7.9.3.1 VREF Voltage Characteristics
        2. 7.9.3.2 VREF Electrical Characteristics
      4. 7.9.4 Analog VBOOST Specification
        1. 7.9.4.1 Analog Mux VBOOST
      5. 7.9.5 Temperature Sensor
    10. 7.10 Serial Interface Specifications
      1. 7.10.1 UART
        1. 7.10.1.1 UART
      2. 7.10.2 I2C
        1. 7.10.2.1 I2C Characteristics
        2. 7.10.2.2 I2C Filter
        3. 7.10.2.3 I2C Timing Diagram
      3. 7.10.3 SPI
        1. 7.10.3.1 SPI
        2. 7.10.3.2 SPI Timing Diagram
      4. 7.10.4 CAN
        1. 7.10.4.1 CAN
      5. 7.10.5 QSPI
        1. 7.10.5.1 QSPI
        2. 7.10.5.2 QSPI Timing Diagram
      6. 7.10.6 I2S/TDM
        1. 7.10.6.1 Serial Audio
        2. 7.10.6.2 I2S/TDM Timing Diagram
    11. 7.11 Digital IO
    12. 7.12 TRNG
      1. 7.12.1 TRNG Electrical Characteristics
      2. 7.12.2 TRNG Switching Characteristics
    13. 7.13 Emulation and Debug
      1. 7.13.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Arm Cortex-M33 core with TrustZone and FPU
    2. 8.2  Power Management and Clock Unit (PMCU)
      1. 8.2.1 Power Management Unit (PMU)
      2. 8.2.2 Clock Module (CKM)
      3. 8.2.3 Operating Modes
        1. 8.2.3.1 Functionality by Operating Mode
    3. 8.3  Device Memory Map
      1. 8.3.1 Memory Organization
      2. 8.3.2 Peripheral Memory Map
    4. 8.4  NVIC Interrupt Map
    5. 8.5  Embedded Flash Memory
    6. 8.6  Embedded SRAM
    7. 8.7  DMA
    8. 8.8  Event Manager
    9. 8.9  Error Aggregator Module (EAM)
    10. 8.10 GPIO
    11. 8.11 IOMUX
      1. 8.11.1 Input/Output Diagrams
    12. 8.12 Analog Modules
      1. 8.12.1 HSADC
      2. 8.12.2 COMP
      3. 8.12.3 Temperature Sensor
      4. 8.12.4 VREF
      5. 8.12.5 Device Analog Connections
    13. 8.13 Security and Cryptography
      1. 8.13.1 Global Security Controller (GSC)
      2. 8.13.2 AESADV
      3. 8.13.3 SHA256
      4. 8.13.4 Public Key Algorithm (PKA)
      5. 8.13.5 TRNG
      6. 8.13.6 Keystore
      7. 8.13.7 CRC
    14. 8.14 Serial Communication Interfaces
      1. 8.14.1 UNICOMM (UART/I2C/SPI)
        1. 8.14.1.1 UART (UNICOMM)
        2. 8.14.1.2 I2C (UNICOMM)
        3. 8.14.1.3 SPI (UNICOMM)
      2. 8.14.2 CAN-FD
      3. 8.14.3 Quad SPI (QSPI)
      4. 8.14.4 Digital Audio Interface - I2S/TDM
    15. 8.15 LFSS
    16. 8.16 Timers, RTC and Watchdogs
      1. 8.16.1 Timers (TIMx)
      2. 8.16.2 RTC_A
      3. 8.16.3 IWDT
      4. 8.16.4 WWDT
    17. 8.17 Serial Wire Debug Interface
    18. 8.18 Bootstrap Loader (BSL)
    19. 8.19 Device Factory Constants
    20. 8.20 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.8.3 System Phase Lock Loop (SYSPLL)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSYSPLLREF SYSPLL reference frequency range 4 48 MHz
fVCO VCO output frequency 160 400 MHz
fSYSPLL SYSPLL output frequency range (1) SYSPLLCLK0, SYSPLLCLK1 5 160 MHz
DCPLL SYSPLL output duty cycle fSYSPLLREF=32MHz, fVCO=320MHz, SYSPLLCLK0/1 45 55 %
JitterSYSPLL SYSPLL RMS cycle-to-cycle jitter PDIV=2, Loop clock=8MHz,fSYSPLLREF=32MHz, fVCO=320MHz 43 ps
SYSPLL RMS period jitter 32
ISYSPLL SYSPLL current consumption fSYSPLLREF=32MHz, fVCO=320MHz, PDIV=2; SYSPLL =160 MHz 1300 uA
tstart,  SYSPLL SYSPLL start-up time fSYSPLLREF=32MHz, fVCO=320MHz, PDIV=2; SYSPLL =160 MHz, ±0.5% accuracy 25 us
(1) The SYSPLL may support higher output frequencies than the device clock system supports.  Ensure that the device maximum frequency specifications are not violated when configuring the SYSPLL output frequencies.