SLAU367P October 2012 – April 2020
Comparator_E Control Register 2
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CEREFACC | CEREFL | CEREF1 | |||||
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CERS | CERSEL | CEREF0 | |||||
| rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 | rw-0 |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | CEREFACC | RW | 0h | Reference accuracy. A reference voltage is requested only if CEREFL > 0.
0b = Static mode 1b = Clocked (low power, low accuracy) mode |
| 14-13 | CEREFL | RW | 0h | Reference voltage level
00b = Reference amplifier is disabled. No reference voltage is requested. 01b = 1.2 V is selected as shared reference voltage input 10b = 2.0 V is selected as shared reference voltage input 11b = 2.5 V is selected as shared reference voltage input |
| 12-8 | CEREF1 | RW | 0h | Reference resistor tap 1. This register defines the tap of the resistor string while CEOUT = 1. |
| 7-6 | CERS | RW | 0h | Reference source. This bit define if the reference voltage is derived from VCC or from the precise shared reference.
00b = No current is drawn by the reference circuitry. 01b = VCC applied to the resistor ladder 10b = Shared reference voltage applied to the resistor ladder. 11b = Shared reference voltage supplied to VCCREF. Resistor ladder is off. |
| 5 | CERSEL | RW | 0h | Reference select. This bit selects to which terminal the VCCREF is applied.
When CEEX = 0: 0b = When CEEX = 0: VREF is applied to the V+ terminal; When CEEX = 1: VREF is applied to the V– terminal 1b = When CEEX = 0: VREF is applied to the V– terminal; When CEEX = 1: VREF is applied to the V+ terminal |
| 4-0 | CEREF0 | RW | 0h | Reference resistor tap 0. This register defines the tap of the resistor string while CEOUT = 0. |