SLLSFT1 October   2026 TIOM2212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  L+ Supply Controller
        1. 7.3.1.1 Auto-retry feature
        2. 7.3.1.2 Current sense feature
      2. 7.3.2  C/Q Transceiver
        1. 7.3.2.1 CQ Driver Fault Detection
        2. 7.3.2.2 CQ Reverse Polarity Protection
        3. 7.3.2.3 CQ Current Source or Sink
        4. 7.3.2.4 CQ Receiver Output
        5. 7.3.2.5 CQ Receiver Threshold
        6. 7.3.2.6 CQ/RX Receiver Glitch Filter
      3. 7.3.3  High-side Switch (HSS) Gate Driver
      4. 7.3.4  DI Receiver
      5. 7.3.5  Reverse Polarity Protection
      6. 7.3.6  Thermal Warning and Shutdown
      7. 7.3.7  Clocking
      8. 7.3.8  Power Up Sequence (TIOM2212)
      9. 7.3.9  Device Functional Modes
        1. 7.3.9.1 IO-Link PHY Mode
          1. 7.3.9.1.1 Integrated Automated Sequences
        2. 7.3.9.2 UART Mode
        3. 7.3.9.3 Frame Handler Mode
        4. 7.3.9.4 Extended Frame Handler Mode
      10. 7.3.10 SPI Communication
      11. 7.3.11 SPI Modes and Frame Formats
      12. 7.3.12 Memory and Registry Maps
        1. 7.3.12.1 device Registers
        2. 7.3.12.2 channel Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.9.1 IO-Link PHY Mode

The IO-Link PHY Mode is the basic PHY driver mode, in which the CQ is directly controlled using the TX and TXEN pins. In this mode, the C/Q driver can be configured to select the source of TX and TXEN based on the PHY Mode configuration register CQSRC in the corresponding channel register.

CQSRC TXD Source TXEN Source
0 (SPI Mode) CQ_TXD field in IOLINK_PHY register CQ_MD field in IOLINK_PHY register
1 (Pin Mode) TXD pin TXEN pin

In both the SPI and PIN sub-modes of this mode, the RXCQ pin acts as the RXD for that channel, if that pin is selected as RXD using the LED4_SEL field in the HSS_ALT_FUNC_SEL register.

In the PIN sub-mode, the CQ_MD field in IOLINK_PHY register is used to configure the CQ driver mode of operation. In the SPI sub-mode, the CQ_MD field in IOLINK_PHY register is used to configure the driver.

Pin Mode

In the PIN sub-mode, the value of CQ_TXD field in IOLINK_PHY register is ignored.

CQ_MD TXEN pin TXD pin CQ

RXCQ pin | CQ_RXD register field

~CQ

[LED4_SEL = 0 & CQ_RX_VTH_DIS != 11]
00 X X HiZ ~CQ
01 (NPN) 0 0 HiZ ~CQ
01 (NPN) 0 1 HiZ ~CQ
01 (NPN) 1 0 HiZ ~CQ
01 (NPN) 1 1 Low ~CQ
10 (PNP) 0 0 HiZ ~CQ
10 (PNP) 0 1 HiZ ~CQ
10 (PNP) 1 0 High ~CQ
10 (PNP) 1 1 HiZ ~CQ
11 (Push Pull) 0 0 HiZ ~CQ
11 (Push Pull) 0 1 HiZ ~CQ
11 (Push Pull) 1 0 High ~CQ
11 (Push Pull) 1 1 Low ~CQ

Note: when LED4_SEL = 0 & CQ_RX_VTH_DIS == 11, then RXCQ is undefined.

SPI Mode

In the SPI sub-mode, the values of TX & TXEN pins are ignored.

CQ_MD CQ_TXD CQ

RXCQ pin| CQ_RXD register field

[LED4_SEL = 0 & CQ_RX_VTH_DIS != 11]
00 X HiZ ~CQ
01 (NPN) 0 HiZ ~CQ
01 (NPN) 1 Low ~CQ
10 (PNP) 0 High ~CQ
10 (PNP) 1 HiZ ~CQ
11 (Push Pull) 0 High ~CQ
11 (Push Pull) 1 Low ~CQ

Note: when LED4_SEL = 0 & CQ_RX_VTH_DIS == 11, then RXCQ is undefined.