SLLSFT1 October   2026 TIOM2212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  L+ Supply Controller
        1. 7.3.1.1 Auto-retry feature
        2. 7.3.1.2 Current sense feature
      2. 7.3.2  C/Q Transceiver
        1. 7.3.2.1 CQ Driver Fault Detection
        2. 7.3.2.2 CQ Reverse Polarity Protection
        3. 7.3.2.3 CQ Current Source or Sink
        4. 7.3.2.4 CQ Receiver Output
        5. 7.3.2.5 CQ Receiver Threshold
        6. 7.3.2.6 CQ/RX Receiver Glitch Filter
      3. 7.3.3  High-side Switch (HSS) Gate Driver
      4. 7.3.4  DI Receiver
      5. 7.3.5  Reverse Polarity Protection
      6. 7.3.6  Thermal Warning and Shutdown
      7. 7.3.7  Clocking
      8. 7.3.8  Power Up Sequence (TIOM2212)
      9. 7.3.9  Device Functional Modes
        1. 7.3.9.1 IO-Link PHY Mode
          1. 7.3.9.1.1 Integrated Automated Sequences
        2. 7.3.9.2 UART Mode
        3. 7.3.9.3 Frame Handler Mode
        4. 7.3.9.4 Extended Frame Handler Mode
      10. 7.3.10 SPI Communication
      11. 7.3.11 SPI Modes and Frame Formats
      12. 7.3.12 Memory and Registry Maps
        1. 7.3.12.1 device Registers
        2. 7.3.12.2 channel Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.1.1 Auto-retry feature

LP_CFG0 register settings can be used to configure the L+ supply current limits. LP_TSC and LP_TAR set the current fault blanking time and auto-recovery time, respectively. LP_AR_DIS controls the auto-recovery behavior. If current through the L+ path exceeds the ILIM set by LP_CLIM bits, then an overcurrent fault is generated. The controller periodically rechecks if the output is still in a current limited condition. In this condition, the device is switched on for LP_TSC and switched off for LP_TAR.

To further reduce the power dissipated in the NFET transistors during turn-on of loads that require large inrush currents (e.g., capacitive loads), the current limiter includes a dynamic blanking time mode that reduces the blanking time when the voltage across the NFET is high, limiting the pulse energy during the initial turn-on phase. Dynamic blanking time mode is operational when the L+ output voltage is below 7V and must be enabled by setting the LP_DYBL_EN bit in the LP_CFG1 register.