SLLSFT1 October   2026 TIOM2212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  L+ Supply Controller
        1. 7.3.1.1 Auto-retry feature
        2. 7.3.1.2 Current sense feature
      2. 7.3.2  C/Q Transceiver
        1. 7.3.2.1 CQ Driver Fault Detection
        2. 7.3.2.2 CQ Reverse Polarity Protection
        3. 7.3.2.3 CQ Current Source or Sink
        4. 7.3.2.4 CQ Receiver Output
        5. 7.3.2.5 CQ Receiver Threshold
        6. 7.3.2.6 CQ/RX Receiver Glitch Filter
      3. 7.3.3  High-side Switch (HSS) Gate Driver
      4. 7.3.4  DI Receiver
      5. 7.3.5  Reverse Polarity Protection
      6. 7.3.6  Thermal Warning and Shutdown
      7. 7.3.7  Clocking
      8. 7.3.8  Power Up Sequence (TIOM2212)
      9. 7.3.9  Device Functional Modes
        1. 7.3.9.1 IO-Link PHY Mode
          1. 7.3.9.1.1 Integrated Automated Sequences
        2. 7.3.9.2 UART Mode
        3. 7.3.9.3 Frame Handler Mode
        4. 7.3.9.4 Extended Frame Handler Mode
      10. 7.3.10 SPI Communication
      11. 7.3.11 SPI Modes and Frame Formats
      12. 7.3.12 Memory and Registry Maps
        1. 7.3.12.1 device Registers
        2. 7.3.12.2 channel Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.9.4 Extended Frame Handler Mode

In extended frame handler mode, the device can send and receive IO-Link standard defined UART frames. This mode provides the user with flexibility to implement extended message features. It comes with a 128-byte integrated buffer and can be used to send and receive messages of any length with the help of provided interrupts.

Operation

Configure the channel into extended frame handler mode by setting the CLMD = 11 in the LCFG register. To transmit a message, fill the TX buffer by writing into the FH_DATA register with the message bytes to transfer. Once the entire message is transmitted, the extended frame handler changes to receive mode and fills the RX buffer for the messages received. At a given time, the TX buffer and RX buffer can hold 128-bytes of data.

User can configure the TX_BTLVL and RX_BTLVL registers with valid values less than or equal to value 128 to enable the TX_BLVL_FBTL and RX_BLVL_RATL interrupts. The TX_BLVL_FBTL interrupt is set when the TX buffer level falls below the configured trigger level, and the RX_BLVL_RATL interrupt is set when the RX buffer level rises above the configured trigger level. The TX_BEMPTY interrupt indicates that the TX buffer is empty, and the RX_BFULL interrupt indicates that the RX buffer is full. If the RX buffer is full and still there is data being received in the CQ interface, OR_ERR is set to indicate that there is a UART overrun error. If the transmitted message is not reflecting on the CQ line, TX_ERR interrupt is set to indicate that there is a transmission error. If the RX frame contains either a parity or frame error, the RX_ERR interrupt is set.

Note: None of the frame handler features are enabled in this extended frame handler mode to provide full flexibility to the user.

CQ OC, LP OC, HSS OC & Reverse Polarity Auto Recovery

The auto recovery feature helps the device to recover from temporary faults, with the help of disable and re-enable cycles. In all CQ, LP, HSS overcurrent and HSS reverse polarity fault conditions, if the fault condition exists for t > tSC (blanking time), the device will detect a fault. In the case that auto recovery is disabled, the status and interrupt registers will reflect the fault status, but the device will not disable the driver until a TSD fault occurs. When auto recovery is enabled, based on the count value in the CQ_DRV_MAX_AR, LP_MAX_AR, HSS_MAX_AR registers, auto recovery will be attempted. If the count value is 0, auto recovery will be attempted indefinitely, and otherwise, the auto recovery will be attempted for the count value.

Once auto recovery fails the number of attempts in these registers, this feature must be disabled and re-enabled by configuring the CQ_DRV_AR_DIS, LP_AR_DIS and HSS_AR_DIS bits. Only after configuring these bits, will the corresponding driver be re-enabled.

LED Driver

The device integrates NPN LED drivers, suitable for widely used common anode RGB LEDs. The device is equipped with PWM (pulse width) and IDRV (max current) configurability to control the output average current, in order to achieve the required colors.

PWM frequency = 225Hz

Config Exponential DC Scaling % On Time (S) Off Time (S) Avg Current (mA) IDRV = 2mA Avg Current (mA) IDRV = 8mA Avg Current (mA) IDRV = 14mA Avg Current (mA) IDRV = 20mA
0 0 0.00E+00 4.44E-03 0 0 0 0
1 1.4 6.21E-05 4.38E-03 0.027954102 0.111816406 0.195678711 0.279541016
2 1.8 7.98E-05 4.36E-03 0.035888672 0.143554688 0.251220703 0.358886719
3 2.5 1.11E-04 4.33E-03 0.049926758 0.199707031 0.349487305 0.499267578
4 3.4 1.51E-04 4.29E-03 0.067993164 0.271972656 0.475952148 0.679931641
5 4.6 2.04E-04 4.24E-03 0.091918945 0.367675781 0.643432617 0.919189453
6 6.3 2.80E-04 4.16E-03 0.125976563 0.50390625 0.881835938 1.259765625
7 8.6 3.82E-04 4.06E-03 0.17199707 0.687988281 1.203979492 1.719970703
8 11 4.89E-04 3.96E-03 0.219970703 0.879882813 1.539794922 2.199707031
9 16 7.11E-04 3.73E-03 0.319946289 1.279785156 2.239624023 3.199462891
10 22 9.78E-04 3.47E-03 0.439941406 1.759765625 3.079589844 4.399414063
11 29 1.29E-03 3.16E-03 0.579956055 2.319824219 4.059692383 5.799560547
12 40 1.78E-03 2.67E-03 0.799926758 3.199707031 5.599487305 7.999267578
13 54 2.40E-03 2.04E-03 1.079956055 4.319824219 7.559692383 10.79956055
14 74 3.29E-03 1.16E-03 1.479980469 5.919921875 10.35986328 14.79980469
15 100 4.44E-03 0.00E+00 2 8 14 20

Faults/Interrupts/Status Handling

All interrupts are logged by default in the corresponding IREQ register at the rising edge of that event . The effect of the IREQ register on the IRQ pin is controlled by the corresponding IMASK register. For example, the CLIREQ logs all listed interrupts, but its effect on the IRQ pin is enabled and disabled using the CLIMASK register.

S No Category Sub Category Acronym Description Interrupt Clear Method
1 Device Fault Fault VCC_OV VCC Over Voltage Clear on Read
2 Fault VCC_WARN VCC Warning Clear on Read
3 Fault VCC_UVLO VCC Undervoltage Clear on Read
4 Channel Fault Fault OT_FAULT Channel level over temperature fault Clear on Read
5 Status OT_WARN Channel level over temperature warning Clear on Read
6 Fault CQ_OC CQ driver overcurrent Clear on Read
7 Fault LP_OC Lplus supply overcurrent Clear on Read
8 Fault LP_UVLO Lplus supply undervoltage lockout Clear on Read
9 Fault CQx_AR CQ Overcurrent auto recovery failed after max retries Clear on Read
10 Fault LPx_AR LP Overcurrent auto recovery failed after max retries Clear on Read
11 Fault HSSx_AR HSS Overcurrent or Reverse Polarity auto recovery failed after max retries Clear on Read
12 Channel Interrupt - PHY Interrupt CQ_F CQ Fell Clear on Read
13 Interrupt CQ_R CQ Rose Clear on Read
14 Interrupt DI_F DI Fell Clear on Read
15 Interrupt DI_R DI Rose Clear on Read
16 Interrupt ASEQ_OK Wake pulse Generated Clear on Read
17 Error RPD_ERR Establish Communication Sequence Error Clear on Read
18 Error WPG_ERR Establish Communication Sequence Complete Clear on Read
19 Error ECS_ERR

Establish Communication Sequence Error

* ECS No response

 Clear on Read
20 Status CQ_RXD CQ RXD level
21 Status DI_RXD DI RXD level
22 Status TXD TXD level
23 Status TXEN TXEN level
24 Channel Interrupt - UART Interrupt RX_RDY Received Byte Ready

Clear if RX Buffer is empty or

Clear on read
25 Interrupt TX_RDY Transmitter Ready

Clear if TX not ready or

Clear on read
26 Error OR_ERR Overrun Error Clear on Read
27 Error RX_ERR Parity or Frame Error Clear on Read
28 Error TX_ERR Transmission Error (Tx Byte != CQ Byte) Clear on Read
29 Channel Interrupt - FH Interrupt MSG_RDY IOLINK Message Ready for Reading

Clear if RX Buffer is empty or

Clear on read
30 Interrupt BLVL_RT

Buffer Level Reached configured trigger level

(Combined TX & RX Buffer level trigger)

Note: To disable specific tx or rx trigger, use a trigger value greater than 128

Clear if rx buffer is below configured level or

Clear if tx buffer level is above configured level or

Clear on read
31 Interrupt SOR Start of Reception Clear on Read
32 Interrupt SOT Start of Transmission Clear on Read
33 Interrupt TBUF_EMTY_AT_CT_EXP Transmit Buffer Empty at Cycle Timer Expiry Clear on Read
34 Error CKSM_ERR Checksum Error Clear on Read
35 Error T1_TA_T2_TO_ERR Response Time tA or Frame Delay t1 or t2 Timeout Error Clear on Read
36 Error TRX_ERR

Transmission or Reception Error

* TX Byte != CQ Byte

* Parity or Frame Error

 Clear on Read
37 Status STATE

FSM State

* IDLE

* TXING

* RXING
38 Channel Interrupt - EFH Error TX_ERR Transmission Error (Tx Byte != CQ Byte) Clear on Read
39 Error RX_ERR Parity or Frame Error Clear on Read
40 Error OR_ERR Overrun Error (Received CQ message, when RX buffer is full) Clear on Read
41 Interrupt RX_BFULL RX Buffer is full Clear on Read
42 Interrupt TX_BEMPTY TX Buffer is empty Clear on Read
43 Interrupt RX_BLVL_RATL RX Buffer rose above trigger level

Clear if rx buffer fell below configured trigger level or

Clear on Read
44 Interrupt TX_BLVL_FBTL TX Buffer fell below trigger level

Clear if tx buffer rose above configured trigger level or

Clear on Read