SLLSFT1 October   2026 TIOM2212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  L+ Supply Controller
        1. 7.3.1.1 Auto-retry feature
        2. 7.3.1.2 Current sense feature
      2. 7.3.2  C/Q Transceiver
        1. 7.3.2.1 CQ Driver Fault Detection
        2. 7.3.2.2 CQ Reverse Polarity Protection
        3. 7.3.2.3 CQ Current Source or Sink
        4. 7.3.2.4 CQ Receiver Output
        5. 7.3.2.5 CQ Receiver Threshold
        6. 7.3.2.6 CQ/RX Receiver Glitch Filter
      3. 7.3.3  High-side Switch (HSS) Gate Driver
      4. 7.3.4  DI Receiver
      5. 7.3.5  Reverse Polarity Protection
      6. 7.3.6  Thermal Warning and Shutdown
      7. 7.3.7  Clocking
      8. 7.3.8  Power Up Sequence (TIOM2212)
      9. 7.3.9  Device Functional Modes
        1. 7.3.9.1 IO-Link PHY Mode
          1. 7.3.9.1.1 Integrated Automated Sequences
        2. 7.3.9.2 UART Mode
        3. 7.3.9.3 Frame Handler Mode
        4. 7.3.9.4 Extended Frame Handler Mode
      10. 7.3.10 SPI Communication
      11. 7.3.11 SPI Modes and Frame Formats
      12. 7.3.12 Memory and Registry Maps
        1. 7.3.12.1 device Registers
        2. 7.3.12.2 channel Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.4 DI Receiver

The device includes two auxiliary receivers DIA and DIB. These receivers can be enabled by setting bits of DI_RX_VTH_EN = 0b11 in each channel-specific register CQ_DRV_DI_CFG.

These inputs are reverse polarity protected with respect to LP, CQ, LM and VCC.

Each DI receiver implements an internal pull up/down internal current source of 2mA. The direction can be set using the CQ_DRV_DI_CFG register. CQ_SRC_EN/CQ_SNK_EN bits are used to enable the source or sink current sources.

DI receiver thresholds are compliant to the IO-Link standard by default. However, to enable operations for lower LP values, the threshold can be ratiometric with respect to LP by setting the DI_RX_VTH_EN bits (in CQ_DRV_DI_CFG) to 01b. This makes the device's thresholds compatible with the IO-Link standard when L+ >= 18V and will be ratiometric for L+ < 18V. The thresholds can also be set to be compatible with IEC 61131-2 type 2/3 by setting DI_RX_VTH_EN bits (in CQ_DRV_DI_CFG) to 10b.

The noise immunity of the DI Receiver can be improved by setting the bit DI_GFILT_EN in CQ_DRV_DI_CFG register. When the glitch filter is enabled, any glitches <1.8us (typical) are ignored by the RX.