SLOSE88A December   2024  – March 2025 TAS6754-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
        1. 7.3.1.1 Power-Supply Sequence
          1. 7.3.1.1.1 Power-Up Sequence
          2. 7.3.1.1.2 Power-Down Sequence
        2. 7.3.1.2 Device Initialization and Power-On-Reset (POR)
      2. 7.3.2 Serial Audio Port
        1. 7.3.2.1 Left-Justified Timing
        2. 7.3.2.2 I2S Mode
        3. 7.3.2.3 DSP Mode
        4. 7.3.2.4 TDM Mode
        5. 7.3.2.5 SDOUT - Data Output
        6. 7.3.2.6 Device Clocking
          1. 7.3.2.6.1 Clock Rates
          2. 7.3.2.6.2 Clock Halt Auto-recovery
          3. 7.3.2.6.3 Sample Rate on the Fly Change
        7. 7.3.2.7 Clock Error Handling
      3. 7.3.3 Digital Audio Processing
        1. 7.3.3.1 PVDD Foldback
        2. 7.3.3.2 High-Pass Filter
        3. 7.3.3.3 Analog Gain
        4. 7.3.3.4 Digital Volume Control
          1. 7.3.3.4.1 Auto Mute
        5. 7.3.3.5 Gain Compensation Biquads
        6. 7.3.3.6 Low Latency Signal Path
        7. 7.3.3.7 Full Feature Low Latency Path
      4. 7.3.4 Class-D operation and Spread Spectrum Control
        1. 7.3.4.1 1L Modulation
        2. 7.3.4.2 High-Frequency Pulse-Width Modulator (PWM)
        3. 7.3.4.3 Spread Spectrum Control
        4. 7.3.4.4 Gate Drive
        5. 7.3.4.5 Power FETs
      5. 7.3.5 Load Diagnostics
        1. 7.3.5.1 DC Load Diagnostics
          1. 7.3.5.1.1 Automatic DC Load Diagnostics at Device Initialization
          2. 7.3.5.1.2 Automatic DC load diagnostics during Hi-Z or PLAY
          3. 7.3.5.1.3 Manual start of DC load diagnostics
          4. 7.3.5.1.4 Short-to-Ground
          5. 7.3.5.1.5 Short-to-Power
          6. 7.3.5.1.6 Shorted-Load and Open-Load
        2. 7.3.5.2 Line Output Diagnostics
        3. 7.3.5.3 AC Load Diagnostics
          1. 7.3.5.3.1 Operating Principal
          2. 7.3.5.3.2 Stimulus
          3. 7.3.5.3.3 Load Impedance
          4. 7.3.5.3.4 Tweeter Detection
        4. 7.3.5.4 Real-Time Load Diagnostics
        5. 7.3.5.5 DC Resistance Measurement
      6. 7.3.6 Protection and Monitoring
        1. 7.3.6.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 7.3.6.2 Overcurrent Shutdown
        3. 7.3.6.3 Current Sense
        4. 7.3.6.4 DC Detect
        5. 7.3.6.5 Digital Clip Detect
        6. 7.3.6.6 Charge Pump
        7. 7.3.6.7 Temperature Protection and Monitoring
          1. 7.3.6.7.1 Overtemperature Shutdown
          2. 7.3.6.7.2 Overtemperature Warning
          3. 7.3.6.7.3 Thermal Gain Foldback
        8. 7.3.6.8 Power Failures
      7. 7.3.7 Hardware Control Pins
        1. 7.3.7.1 FAULT Pin
        2. 7.3.7.2 PD Pin
        3. 7.3.7.3 STBY Pin
        4. 7.3.7.4 GPIO Pins
          1. 7.3.7.4.1 General Purpose Input
          2. 7.3.7.4.2 General Purpose Output
        5. 7.3.7.5 Advanced GPIO functions
          1. 7.3.7.5.1 Clock Synchronization
            1. 7.3.7.5.1.1 External SYNC signal (GPIO sync)
            2. 7.3.7.5.1.2 Synchronization through the audio serial clock (SCLK)
            3. 7.3.7.5.1.3 TAS6754-Q1 as clock source for external devices
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal Reporting Signals
        1. 7.4.1.1 Fault Signal
        2. 7.4.1.2 Warning Signal
      2. 7.4.2 Device States and Flags
        1. 7.4.2.1 Audio Channel States
          1. 7.4.2.1.1 SHUTDOWN State
          2. 7.4.2.1.2 DEEP SLEEP State
          3. 7.4.2.1.3 LOAD DIAG State
          4. 7.4.2.1.4 SLEEP State
          5. 7.4.2.1.5 Hi-Z State
          6. 7.4.2.1.6 PLAY State
          7. 7.4.2.1.7 FAULT State
          8. 7.4.2.1.8 Auto Recovery (AUTOREC) State
      3. 7.4.3 Fault Events
        1. 7.4.3.1 Power Fault Events
          1. 7.4.3.1.1 DVDD Power-On-Reset (POR)
          2. 7.4.3.1.2 DVDD Undervoltage Fault
          3. 7.4.3.1.3 VBAT Overvoltage Fault
          4. 7.4.3.1.4 VBAT Undervoltage Fault
          5. 7.4.3.1.5 PVDD Overvoltage Fault
          6. 7.4.3.1.6 PVDD Undervoltage Fault
        2. 7.4.3.2 Overtemperature Shutdown (OTSD) Event
        3. 7.4.3.3 Overcurrent Limit Fault Event
        4. 7.4.3.4 Overcurrent Shutdown Event
        5. 7.4.3.5 DC Fault Event
        6. 7.4.3.6 Clock Error Event
        7. 7.4.3.7 Charge Pump Fault Event
      4. 7.4.4 Warning Events
        1. 7.4.4.1 Overtemperature Warning Event
        2. 7.4.4.2 Overcurrent Limit Warning Event
        3. 7.4.4.3 Clip Detect Warning Event
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Communication Bus
      2. 7.5.2 I2C Address Selection
      3. 7.5.3 I2C Bus Protocol
      4. 7.5.4 Random Write
      5. 7.5.5 Sequential Write
      6. 7.5.6 Random Read
      7. 7.5.7 Sequential Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Reconstruction Filter Design
    2. 8.2 Typical Application
      1. 8.2.1 BTL Application
      2. 8.2.2 Power Supply Recommendations
      3. 8.2.3 Power Supply Decoupling
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Electrical Connection of Thermal pad and Heat Sink
        2. 8.3.1.2 EMI Considerations
        3. 8.3.1.3 General Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = 14.4V, VBAT = 14.4V, DVDD = 1.8V, RL = 4Ω,
Pout = 1W/ch, ƒout = 1kHz, Fsw = 2.048MHz, AES17 Filter, reconstruction filter inductor used: 3.3µH-VCMT053T-3R3MN5 and 1µF, default I2C settings + start-up script, see application diagram
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IDVDD DVDD supply current All channels playing, -60dB Signal 22 28 mA
All channels playing, -60dB Signal, DVDD = 3.3V 22
IPVDD_IDLE PVDD idle current All channels playing, no audio input, FSW = 2.048MHz 47 60 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input, FSW = 2.048MHz 115 130 mA
IPVDD_Shutdown PVDD shutdown current PD active, DVDD = 0V 4 5 μA
IVBAT_Shutdown VBAT shutdown current PD active, DVDD = 0V 5 7 μA
ITOTAL_Shutdown PVDD+VBAT shutdown current PD active, DVDD = 0V 12 μA
IDVDD_Shutdown DVDD shutdown current PD active, DVDD = 1.8V 1 3 μA
PD active, DVDD = 3.3V 1 3
OUTPUT POWER
PO_BTL Output power per channel, BTL 4Ω, PVDD = 14.4V, THD+N = 1%,TC = 75℃ 21 23 W
4Ω, PVDD = 14.4V, THD+N = 10%,TC = 75℃ 26 30
4Ω, PVDD = 18V, THD+N = 1%,TC = 75℃ 33 37
4Ω, PVDD = 18V, THD+N = 10%,TC = 75℃ 41 46
2Ω, PVDD = 14.4V, THD+N = 1%,TC = 75℃ 37 40
2Ω, PVDD = 14.4V, THD+N = 10%,TC = 75℃ 44 50
EFFP Power efficiency 4 channels operating, 25W output power per channel, RL = 4Ω, PVDD = 14.4V, TC = 25°C; (includes output filter losses) 87 %
AUDIO PERFORMANCE
Vn Output noise voltage Zero input, A-weighting, Gain = -5dB to match PVDD
of 14.4V		 35 μV
G Gain Peak output voltage at full scale digital input 28 V/FS
THD+N Total harmonic distortion + noise 0.03 %
20Hz to 20kHz 0.08 %
FBW Frequency response 20Hz to 20kHz, without LC filter impact or integrated
compensation		 0.5 dB
GMUTE Output attenuation Assert MUTE and compare to amp playing 1W audio into 4Ω 100 dB
Crosstalk Channel crosstalk PVDD = 14.4Vdc, ƒ = 1kHz -90 -80 dB
PSRR Power-supply rejection ratio PVDD = 14.4Vdc + 1VRMS,  ƒ = 1kHz -75 dB
DIGITAL INPUT PINS
VIH Input logic level high 70 %DVDD
VIL Input logic level low 30
IIH Input logic current VI = DVDD 15 µA
IIL VI = 0 -15
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±1mA 90 %DVDD
VOL Output voltage for logic level low 10
VOH Output voltage for logic level high DVDD = 3.3V, I = ±2mA 90 %DVDD
VOL Output voltage for logic level low DVDD = 3.3V, I = ±2mA 10 %DVDD
BYPASS VOLTAGES
VGVDD Gate drive bypass pin voltage 5 V
VAVDD_BYP , VVREG_BYP Analog bypass pins voltage 5 V
VDVDD_BYP, VPLL_BYP, VVR_DIG Digital bypass pins voltage 1.5 V
OVERVOLTAGE (OV) PROTECTION
PVDDOV_SET PVDD overvoltage shutdown set 19.1 20 21 V
PVDDOV_HYS PVDD overvoltage recovery hysteresis 0.5 V
VBATOV_SET VBAT overvoltage shutdown set 19.1 20 22 V
VBATOV_HYS VBAT overvoltage recovery hysteresis 0.5 V
UNDERVOLTAGE (UV) PROTECTION
PVDDUV_SET PVDD undervoltage shutdown set 3.5 4 4.5 V
PVDDUV_HYS PVDD undervoltage  recovery hysteresis 0.5 V
VBATUV_SET VBAT undervoltage shutdown set 3.5 4 4.5 V
VBATUV_HYS VBAT undervoltage recovery hysteresis 0.5 V
DVDDUV_SET DVDD undervoltage shutdown set 1.4 1.59 V
POWER-ON RESET (POR)
VPOR_SET DVDD power on reset set Increasing DVDD 0.9 1.51 V
VPOR_HYS DVDD power on reset recovery hysteresis 0.2 V
VPOR_OFF DVDD power off threshold Decreasing DVDD 0.5 1.3 V
OVERTEMPERATURE (OT) PROTECTION and Temperature Sensing
OTSD(i) Per channel over-temperature shutdown 175 °C
OTW Global junction over-temperature warning 135 °C
OTSD Global junction over-temperature shutdown 155 °C
OTHYS_Global Over-temperature recovery hysteresis 15 °C
OTHYS_Local Over-temperature recovery hysteresis 15 °C
LOAD OVERCURRENT PROTECTION
ILIM Overcurrent cycle-by-cycle limit OC Level 1 2.5 3.5 A
OC Level 2 3.3 4.3
OC Level 3 4.6 5.6
OC Level 4 6.3 6.7
ISD Overcurrent shutdown  OC Level 1, Any short to supply, ground, or other channels 5 A
OC Level 2, Any short to supply, ground, or other channels 6
OC Level 3, Any short to supply, ground, or other channels 8
OC Level 4, Any short to supply, ground, or other channels 9
CLICK AND POP
VCP_Multi Output click and pop voltage ITU-R 2k filter, Hi-Z to PLAY, PLAY to Hi-Z, Multistep turn on, PVDD = 14.4V 5 mV
DC OFFSET
VOFFSET Output offset voltage TC = 50℃ 2 5 mV
DC DETECT
DCFAULT Output DC fault protection 1.4 2 2.5 V
LOAD DIAGNOSTICS
S2P Maximum resistance to detect
a short from OUT pin(s) to
PVDD		 2000 Ω
S2G Maximum resistance to detect
a short from OUT pin(s) to
ground		 200 Ω
SL Shorted load detection tolerance Other channels in Hi-Z ±0.5 Ω
OL
Open Load (OL)
Detection Threshold

 Other channels in Hi-Z 40 Ω
ACIMP AC impedance accuracy ƒ = 18.75kHz, RL = 4Ω, Impedance at output pins ±0.75 Ω
fAC AC diagnostic test frequency Default 18.75 kHz
I2C ADDRESS PIN
tI2C_ADDR Time delay needed for I2C address set-up 300 μs
I2C CONTROL PORT
tBUS Bus free time between start and stop conditions 1.3 μs
th1 Hold Time, SCL to SDA 0 ns
th2 Hold Time, start condition to SCL 0.6 μs
tSTART I2C Startup Time After DVDD Power On Reset 12 ms
tRISE Rise Time, SCL and SDA 300 ns
tFALL Fall Time, SCL and SDA 300 ns
tSU1 Setup, SDA to SCL 100 ns
tSU2 Setup, SCL to Start Condition 0.6 μs
tSU3 Setup, SCL to Stop Condition 0.6 μs
tW(H) Required Pulse Duration SCL "High" 0.6 μs
tW(L) Required Pulse Duration SCL "Low" 1.3 μs
SERIAL AUDIO PORT
DSCLK Allowable input clock duty cycle 45% 50% 55%
fS Supported input sample rates 44.1 192 kHz
fSCLK Supported SCLK frequencies 32 512 xFS
fSCLK_Max Maximum frequency 24.576 MHz
tSCY SCLK pulse cycle time 40 ns
tSCL SCLK pulse-with LOW 16 ns
tSCH SCLK pulse-with HIGH 16 ns
tSF SCLK rising edge to FSYNC edge 8 ns
tFS FSYNC edge to SCLK rising edge 8 ns
tDS DATA set-up time 8 ns
ci Input capacitance, pins SCLK, FSYNC, SDIN_1, SDOUT_1, GPIO_x 10 pF
tDH DATA hold time 8 ns
TAudioLA Audio path latency from input
to output measured in FSYNC sample count		 FSYNC = 44.1kHz or 48kHz 22 samples
FSYNC = 96kHz 23
FSYNC = 192kHz 24
TLLPLA Low latency path latency from
input to output measured in FSYNC sample count		 FSYNC = 44.1kHz or 48kHz 6 samples
FSYNC = 96kHz 7