SLUSFN0A April   2025  – December 2025 BQ25630

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On-Reset (POR)
      2. 8.3.2  Device Power Up from Battery
      3. 8.3.3  USB-C Detection
        1. 8.3.3.1 Legacy Adapter Detection
        2. 8.3.3.2 USB-C Dead Battery Mode
        3. 8.3.3.3 SNK Mode
        4. 8.3.3.4 SRC Mode
        5. 8.3.3.5 DRP Mode - Dual Role Port
        6. 8.3.3.6 USB-C Debug Accessory Detection
      4. 8.3.4  Device Power Up from Input Source
        1. 8.3.4.1 REGN LDO Power Up
        2. 8.3.4.2 D+/D– Detection Sets Input Current Limit
        3. 8.3.4.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 8.3.4.4 Converter Power-Up
        5. 8.3.4.5 Input Current Optimizer (ICO)
        6. 8.3.4.6 Switching Frequency and Dithering Feature
      5. 8.3.5  Power Path Management
        1. 8.3.5.1 Narrow VDC Architecture
        2. 8.3.5.2 Dynamic Power Management
        3. 8.3.5.3 High Impedance (HIZ) Mode
      6. 8.3.6  Battery Charging Management
        1. 8.3.6.1 Autonomous Charging Cycle
        2. 8.3.6.2 Battery Charging Profile
        3. 8.3.6.3 Charging Termination
        4. 8.3.6.4 Thermistor Qualification
          1. 8.3.6.4.1 Advanced Temperature Profile in Charge Mode
          2. 8.3.6.4.2 TS Pin Thermistor Configuration
          3. 8.3.6.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 8.3.6.4.4 JEITA Charge Rate Scaling
        5. 8.3.6.5 Charging Safety Timers
        6. 8.3.6.6 Alternate Power from Input
      7. 8.3.7  USB On-The-Go (OTG)
        1. 8.3.7.1 Boost OTG Mode
      8. 8.3.8  Integrated 12-bit ADC for Monitoring
      9. 8.3.9  Status Outputs (INT , PG )
        1. 8.3.9.1 PG Pin Power Good Indicator
        2. 8.3.9.2 Interrupts and Status, Flag, and Mask Bits
        3. 8.3.9.3 Interrupt to Host (INT)
      10. 8.3.10 BATFET Control
        1. 8.3.10.1 Shutdown Mode
        2. 8.3.10.2 Ship Mode
        3. 8.3.10.3 Standby Mode
        4. 8.3.10.4 System Power Reset
      11. 8.3.11 Protections
        1. 8.3.11.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 8.3.11.1.1 Battery Overcurrent Protection
          2. 8.3.11.1.2 Battery Undervoltage Lockout
        2. 8.3.11.2 Voltage and Current Monitoring in Buck Mode
          1. 8.3.11.2.1 Input Overvoltage
          2. 8.3.11.2.2 System Overvoltage Protection (SYSOVP)
          3. 8.3.11.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 8.3.11.2.4 System Short
          5. 8.3.11.2.5 Battery Overvoltage Protection (BATOVP)
          6. 8.3.11.2.6 Sleep Comparator
        3. 8.3.11.3 Voltage and Current Monitoring in Boost Mode
          1. 8.3.11.3.1 Boost Mode Overvoltage Protection
          2. 8.3.11.3.2 Boost Mode Duty Cycle Protection
          3. 8.3.11.3.3 Boost Mode PMID Undervoltage Protection
          4. 8.3.11.3.4 Boost Mode Battery Undervoltage
          5. 8.3.11.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 8.3.11.3.6 Boost Mode SYS Short
        4. 8.3.11.4 Thermal Regulation and Thermal Shutdown
          1. 8.3.11.4.1 Thermal Protection in Buck Mode
          2. 8.3.11.4.2 Thermal Protection in Boost Mode
          3. 8.3.11.4.3 Thermal Protection in Battery-only Mode
        5. 8.3.11.5 Liquid Detection and Corrosion Mitigation (Patent Pending)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 START and STOP Conditions
        3. 8.5.1.3 Byte Format
        4. 8.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.5.1.5 Target Address and Data Direction Bit
        6. 8.5.1.6 Single Write and Read
        7. 8.5.1.7 Multi-Write and Multi-Read
    6. 8.6 Register Maps
      1. 8.6.1 Register Programming
      2. 8.6.2 BQ25630 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.4.2 D+/D– Detection Sets Input Current Limit

The device contains a D+/D– based input source detection to set the input current limit automatically. The D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter detections. When an input source is plugged-in and USB-C Default or no USB-C connection is detected, the device starts standard USB BC1.2 detections. The USB BC1.2 is capable of identifying Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard adapter detection is applied to set the input current limit.

When DCP is detected, the device initiates adjustable high voltage adapter handshake. The handshake connects combinations of voltage sources and current sinks on D+/D- to signal input source to raise output voltage from 5V to 9V or 12V if either EN_9V or EN_12V register bits are set to 1. The adjustable high voltage adapter handshake can be disabled by clearing both EN_9V and EN_12V register bits.

Upon the completion of input source type detection, an INT pulse is asserted to the host and the following registers are changed:

  1. Input Current Limit (IINDPM) register is changed to set current limit
  2. VBUS_STAT bits are updated to indicate the detected input source type

After detection completes, the host can over-write the IINDPM register to change the input current limit if needed.


BQ25630 D+/D– Detection Flow

Figure 8-1 D+/D– Detection Flow

If DCP is detected (VBUS_STAT = 011), the device turns on VDP_SRC on D+ if EN_DCP_BIAS is set to 1. Setting EN_DCP_BIAS to 0 while VBUS_STAT = 011 disables the VDP_SRC, and setting EN_DCP_BIAS to 1 while VBUS_STAT = 011 enables the VDP_SRC. The EN_HIZ bit has priority over EN_DCP_BIAS.

The non-standard detection is used to distinguish vendor specific adapters based on unique dividers on the D+/D- pins. During the non-standard detection, no source or sink is applied to either D+ or D- pin. Comparators detect the voltage applied on each pin and determine the input current limit according to Table 8-1.

Table 8-1 Non-Standard Adapter Detection
Non-Standard AdapterD+ ThresholdD– ThresholdInput Current Limit (A)
Divider 1VD+ within VD+D- _2p0VD– within VD+D- _2p81
Divider 2VD+ within VD+D- _2p8VD– within VD+D- _2p02.1
Divider 3VD+ within VD+D- _2p8VD– within VD+D- _2p82.4
Table 8-2 Input Current Limit Setting from D+/D– Detection
D+/D– DetectionInput Current Limit (IINDPM)VBUS_STAT
USB SDP (USB500)500mA1h
USB CDP1.5A2h
USB DCP3.2A3h
Divider 11A5h
Divider 22.1A5h
Divider 32.4A5h
HVDCP1.5A6h
Unknown 5V Adapter 3.2A 4h