SLUSG21A May   2025  – September 2025 UCC25661

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 AC Input Zero Crossing Detection
        3. 7.3.5.3 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Start-up
          1. 7.5.1.1.1 First Time Start-up Sequence
          2. 7.5.1.1.2 Restart Sequence
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

UCC25661 DDB Package, 16-Pin SOIC; Pins 2 and 13 Removed (Top View)Figure 5-1 DDB Package, 16-Pin SOIC; Pins 2 and 13 Removed (Top View)
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NAMENO.
HV1I

High-voltage (HV) start-up and X-capacitor discharge.

The HV pin is used to perform HV start-up. After start-up is completed, the HV pin is used for AC presence detection and X-capacitor discharge. This pin is connected to the rectified AC line or input bulk capacitor.

2—Missing. HV spacer for creepage between high voltage and low voltage pins
BLK3I

Bulk DC voltage sensing and input for feedforward control.

Connect BLK through a resistor divider between positive terminal of bulk capacitor and GNDP to set the LLC converter start and stop voltage thresholds. See Section 7.3.5.1 for more details.

OVP/OTP4I

Overvoltage protection and external over-temperature protection input.

Connect OVP/OTP to GNDP through an NTC resistor and to VCCP through zener diode. See Section 7.3.5.3 for more details.

FB5I

Feedback control input.

Connect FB to the collector pin of an optocoupler in the isolated feedback network. See Section 7.3.3 for more details.

LL6I

Light load operation and burst mode threshold setting input.

Connect LL to the center node of resistor divider between V5P an GNDP. The impedance and voltage at LL pin is used to select the thresholds for high frequency and low frequency burst mode operation. See Section 7.5.3 for more details.

TSET7I/O

VCR synthesizer time constants setting input and PFC on/off output.

TSET is used to set the minimum VCR time constants and the minimum switching frequency in IPPC mode by using a resistor divider as defined in Section 8.2.2.18. TSET also dual functions at the PFC disable pin and as an input to enforce low-frequency burst mode. See Section 8.2.2.18 for details.
V5P8P

5V Internal Regulator Output.

Connect a decoupling capacitor (recommend 1uF to 4.7uF) from V5P to GNDP. Place this capacitor close to the V5P. Chose the dielectric based on application need.

ISNS9I

Resonant Circuit Current Sense Input.

Connect ISNS pin to resonant capacitor through a series differentiator capacitor and a current sense resistor to GNDP.

This pin senses the differentiated resonant capacitor voltage. This signal is internally used to:

  • Generate the control signal
  • OCP and cycle-by-cycle current limiting
  • Capacitive region avoidance

See Section 8.2.2.17 for more details.

GNDP10PGround reference pin. Connect GNDP to primary-side bulk capacitor negative terminal.
LO11OLow-side switch gate driver output. Connect to low-side switch gate terminal with a minimal gate drive circuit loop area.
VCCP12P

IC supply voltage pin.

Connect a low-ESR ceramic 2.2µF decoupling capacitor between VCCP and GNDP. A parallel combination of energy storage electrolytic and filter capacitors are typically used in addition.

For applications including an auxiliary bias winding on the LLC transformer, the VCCP pin is connected through a diode to the bias winding. For applications where HV start-up is disabled, VCCP is supplied by an auxiliary bias supply.

VCCP pin is internally clamped to 19V.

13N/AMissing pin. High-voltage spacer for creepage between high-voltage and low-voltage pins.
HB14P

High-side gate driver bias input. Connect a capacitor (minimum of 0.1µF, maximum of 5µF) between HB and HS pins. See Section 8.3.2 for more details.

HO15OHigh-side switch gate driver output. Connect to high-side switch gate terminal with a minimal gate drive circuit loop area.
HS16P

High-side gate driver return path and switching node connection input. Connect to the switching node of the half-bridge structure of the LLC converter. The voltage at this pin used to determine the adaptive dead time. See Section 7.3.4 for more details.

Please refer to section Section 8.2 for more details.