SLUSG21A May   2025  – September 2025 UCC25661

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 AC Input Zero Crossing Detection
        3. 7.3.5.3 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Start-up
          1. 7.5.1.1.1 First Time Start-up Sequence
          2. 7.5.1.1.2 Restart Sequence
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.18 TSET Pin

The TSET pin resistors set the VCR integrator time constants (Timer gain [ks] , RVCR, RRAMP, CVCR) and the minimum switching frequency in IPPC mode. The TSET pin resistors also determine the VFBreplica voltage for a given output power.

The following information is for devices with OCP/OLP decoupling enabled.

Choose VTSETB voltage option based on fSW(Mgmin) and the full load operating frequency at the minimum input voltage and maximum output power. For this design, option 4 is selected in the design calculator because the observed full load operating frequency is 89kHz at the minimum input voltage of 365V and at the rated output power. For option #4, VTSETB voltage must be between 0.742V and 48mV, as provided in Table 7-1.

Choose (VTSETA-VTSETB) voltage to set the FBReplica magnitude for a given power output. Choose the difference voltage so that, at maximum output power, the FBReplica magnitude is below VFBOLP, as shown in Figure 8-2 with the required margin as the worst case. For this design, option #5 is selected from the Table 7-1 table so that VCR integrator time constants along with chosen ISNS and BLK resistors makes the FBReplica magnitude close to 4V at the maximum input power and set the (VTSETA-VTSETB) voltage between 0.850V and 48mV.Table 7-1.

Equation 62. V T S E T B = R T S E T _ l o w e r ∙ V 5 P R T S E T _ l o w e r + R T S E T _ u p p e r
Equation 63. V T S E T A = V T S E T B + R T S E T _ l o w e r ∙ R T S E T _ u p p e r R T S E T _ l o w e r + R T S E T _ u p p e r ∙ I T S E T P r g m

By solving Equation 62 and Equation 63, RTSET_upper is 572.78kΩ and RTSET_lower is 99.81kΩ.

Finally, RTSET_upper = 576kΩ and RTSET_lower = 100kΩ are chosen.

Final VTSETB and (VTSETA-VTSETB) are calculated using Equation 64 and Equation 65:

Equation 64. V T S E T B = 100 k ∙ 5 V 100 k + 576 k = 0.74 V
Equation 65. ( V T S E T A - V T S E T B ) = 100 k ∙ 576 k 100 k + 576 k ∙ 10 μ A = 0.852 V

Figure 8-2 shows the FBReplica voltage regarding the input power of the LLC.

To calculate Pin, 92% efficiency is used in the following equation.

Equation 66. P i n = P o u t η
UCC25661 FBReplica versus Pin Figure 8-2 FBReplica versus Pin

Measure the FBReplica voltage by inserting a 10kΩ resistor between the feedback optocoupler emitter and ground. Assume the voltage measured on the 10kΩ resistor is V10k. Use Equation 67 to calculate the FBReplica voltage:

Equation 67. F B Re p l i c a = I F B − V 10 k Ω 10 k Ω × R F B I n t e r n a l