SLUSG21A May   2025  – September 2025 UCC25661

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
        1. 7.3.2.1 TSET Programming
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brownin and Brownout Thresholds and Options
        2. 7.3.5.2 AC Input Zero Crossing Detection
        3. 7.3.5.3 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Start-up
          1. 7.5.1.1.1 First Time Start-up Sequence
          2. 7.5.1.1.2 Restart Sequence
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Thresholds Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.20 Burst Mode Programming

The LL pin voltage (VLLB) and the resistor divider that connects to the LL pin allow the user to set the HFBurstEntry and LFBurstEntry thresholds as shown below.

Equation 78. V L L B = R L L _ l o w e r ⋅ V 5 P R L L _ u p p e r + R L L _ l o w e r
Equation 79. V L L A = V L L B + R L L _ l o w e r R L L _ u p p e r R L L _ u p p e r + R L L _ l o w e r ⋅ I L L P r g m

As shown in Table 7-1, (VLLA – VLLB) voltage determines the VLLB/HFBurstEntry ratio

For this design, (VLLB/HFBurstEntry) = 0.55 is considered. Confirm that the (VLLA-VLLB) value is between 1.087V and 1.391V.

Then HFBurstEntry is related to LL pin voltage as below:

Equation 80. H F B u r s t E n t r y = V L L B 0.55 = 1.818 ⋅ V L L B

The LFBurstEntry is always related to LL pin voltage as below:

Equation 81. L F B u r s t E n t r y = V L L B 0.6 = 1.667 ⋅ V L L B

Based on curve and hardware testing, adjust VLLB and (VLLA – VLLB) to meet the desired performance.

For this design, VLLB = 1.2V and VLLA = (Max voltage of (VLLA – VLLB)) – 0.1V are considered. By substituting these values in Equation 78, Equation 79, RLLupper is 538k and RLLlower is 170k.

Finally RLLupper = 536kΩ and RLLlower = 169kΩ are chosen for this design.

The final burst entries are calculated as:

Equation 82. V L L B = 169 k ⋅ 5 169 k + 536 k = 1.199 V
Equation 83. V L L A = 1.199 V + 169 k ⋅ 536 k 169 k + 536 k ⋅ 10 μ A = 2.483 V
Equation 84. V L L A − V L L B = 1.285 V
Equation 85. H F B u r s t E n t r y = 1.818 ⋅ 1.199 = 2.179 V
Equation 86. L F B u r s t E n t r y = 1.667 ⋅ 1.199 = 1.998 V