SLVSHI9A March   2025  – September 2025 TPS7H5020-SEP , TPS7H5020-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN) and VLDO
      2. 7.3.2  Driver Input Voltage (PVIN)
      3. 7.3.3  Start-Up
      4. 7.3.4  Enable and Undervoltage Lockout (UVLO)
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Output Voltage Programming
      8. 7.3.8  Soft Start (SS)
      9. 7.3.9  Switching Frequency and External Synchronization
        1. 7.3.9.1 Internal Oscillator Mode
        2. 7.3.9.2 External Synchronization Mode
          1. 7.3.9.2.1 External Synchronization with TPS7H5021
      10. 7.3.10 Duty Cycle Limit
      11. 7.3.11 Minimum On-Time and Off-Time
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Leading Edge Blank Time
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Gate Driver Output
      16. 7.3.16 Unpowered Voltage Clamp
      17. 7.3.17 Sourcing Driver Return (OUTH_REF)
      18. 7.3.18 Slope Compensation (RSC)
      19. 7.3.19 Frequency Compensation
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistor Selection
        3. 8.2.2.3  Driver PVIN Configuration
        4. 8.2.2.4  Soft-Start Capacitor Selection
        5. 8.2.2.5  Transformer Design
        6. 8.2.2.6  Primary Power Switch Selection
        7. 8.2.2.7  Output Diode Selection
        8. 8.2.2.8  RCD Clamp
        9. 8.2.2.9  Output Capacitance Selection
        10. 8.2.2.10 Current Sense Resistor
        11. 8.2.2.11 Frequency Compensation Component Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Boost Converter
      5. 8.2.5 Feedback Isolation Using ISOS510
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1 Input Voltage (VIN) and VLDO

During steady state operation, the input voltage of the TPS7H502x must be between 4.5V and 14V. A minimum bypass capacitance of at least 0.1µF is needed between VIN and AGND. The input bypass capacitors should be placed as close to the controller as possible. A resistor divider connected between VIN, EN, and GND can be used to adjust the input voltage UVLO.

The voltage applied at VIN serves as the input for the internal regulator that generates the voltage at VLDO. The VLDO output is programmable from 4.5V to 5.5V. This allows for connecting VLDO to PVIN and driving GaN power semiconductor devices using the controller. When programming VLDO, the resistor divider consists of two resistors: RVT between VLDO and VLDO_FB, and RVB between VLDO_FB and AGND. Equation 1 can be used to select the proper RVB resistor.

Equation 1. RVB=VREFCAPVLDO- VREFCAP×RVT

where:

  • VREFCAP is 1.223V (typical)
  • VLDO is the desired output voltage of the internal regulator between 4.5V and 5.5V
  • RVT is the value of the top resistor, between VLDO and VLDO_FB, selected by the user (i.e. 10kΩ)

TPS7H5020-SEP TPS7H5020-SP TPS7H5021-SEP TPS7H5021-SP Configuration for Programming VLDO Output Voltage Figure 7-1 Configuration for Programming VLDO Output Voltage

For applications in which VLDO is not used as the input to the driver stage, it is recommended to select resistors to set VLDO to 5V. The resistors RVT and RVB must always be populated. The maximum dropout voltage for the VLDO regulator is 0.4V. Note that as the headroom voltage increases for the VLDO regulator, its output current capacity also increases until the input voltage reaches 7V. At this point, the full current capability of the VLDO regulator is realized. See the Electrical Characteristics for more details. This becomes critical for applications in which VLDO is used to provide a regulated input voltage at PVIN for driving GaN FETs, as the gate current demanded by the FET is determined by:

Equation 2. I g = Q g × f s w

where:

  • Ig is the gate current of the GaN FET
  • Qg is the total gate charge of the GaN FET (found in the manufacturer's data sheet)
  • fsw is the power converter switching frequency

The external current to be supplied to the FET by VLDO in this scenario should not exceed the capability of the regulator. The recommended capacitance to be connected at VLDO is 1µF. The EN pin of the device can also be tied to VLDO.