The TPS7H502x includes a voltage clamp on the gate driver output. This clamp is active only when VIN is less than approximately 2V. With low voltage on VIN, the internal OUTL driver is not adequately powered and thus is incapable of actively pulling the driver output low. This potentially leaves the driver output in a high-impedance state, and the unpowered voltage clamp was added to mitigate this issue. This unpowered clamp is only operational while the controller is disabled.

The bus voltage VBUS of the converter can begin to rise while the controller input VIN is low. Without a sufficiently low impedance between OUTL and PGND, the slew rate (dV/dt) of the bus voltage can cause an unintentional turn-on of the FET through the gate-drain capacitance C_GD. The induced current through C_GD can charge the gate-source capacitance C_GS above the gate-source threshold of the FET, enabling undesired current flow from VBUS to PGND. The unpowered voltage clamp limits the voltage at the gate of the FET until such time as the driver has sufficient voltage and the controller is enabled. The voltage clamp values can be viewed in the Specifications table. After the controller is enabled, the voltage clamp is deactivated and does not interfere with the normal operation of the controller and driver. Note that the criteria for deactivating the clamp are the same as those required for start-up of the device, as outlined in Start-Up. An external pull-down resistor can be used between OUT to PGND as a supplement to the unpowered voltage clamp to further mitigate issues related to unintentional turn-on. A pull-down resistor in the range of 10kΩ to 50kΩ is recommended, if used. Note that the addition of the external resistor slightly increases the quiescent and operating currents for the device, with a smaller resistor causing a larger increase in these currents.