SLVSHI9A March   2025  – September 2025 TPS7H5020-SEP , TPS7H5020-SP

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN) and VLDO
      2. 7.3.2  Driver Input Voltage (PVIN)
      3. 7.3.3  Start-Up
      4. 7.3.4  Enable and Undervoltage Lockout (UVLO)
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Output Voltage Programming
      8. 7.3.8  Soft Start (SS)
      9. 7.3.9  Switching Frequency and External Synchronization
        1. 7.3.9.1 Internal Oscillator Mode
        2. 7.3.9.2 External Synchronization Mode
          1. 7.3.9.2.1 External Synchronization with TPS7H5021
      10. 7.3.10 Duty Cycle Limit
      11. 7.3.11 Minimum On-Time and Off-Time
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Leading Edge Blank Time
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Gate Driver Output
      16. 7.3.16 Unpowered Voltage Clamp
      17. 7.3.17 Sourcing Driver Return (OUTH_REF)
      18. 7.3.18 Slope Compensation (RSC)
      19. 7.3.19 Frequency Compensation
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistor Selection
        3. 8.2.2.3  Driver PVIN Configuration
        4. 8.2.2.4  Soft-Start Capacitor Selection
        5. 8.2.2.5  Transformer Design
        6. 8.2.2.6  Primary Power Switch Selection
        7. 8.2.2.7  Output Diode Selection
        8. 8.2.2.8  RCD Clamp
        9. 8.2.2.9  Output Capacitance Selection
        10. 8.2.2.10 Current Sense Resistor
        11. 8.2.2.11 Frequency Compensation Component Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Boost Converter
      5. 8.2.5 Feedback Isolation Using ISOS510
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Output Capacitance Selection

Generally, there are two different calculations that can be used to determine the output capacitance required for the converter. The first, shown in Equation 62 , determines the amount of output capacitance that is needed to meet the output voltage ripple requirements of the design. The first calculates the amount of capacitance required to meet the maximum allowable voltage deviation at the output in response to a worst-case load transient as shown in Equation 64. Once the two calculations are performed, the maximum of these should be chosen as the output capacitance for the design. The calculations are shown for target voltage ripple of 2% of the output voltage and maximum allowable voltage deviation of 7.5% of the output voltage.

Equation 62. C O U T > I O U T × D M A X V R I P P L E × f S W
Equation 63. C O U T > 4 A × 0.35 100 m V × 500 k H z = 28 µ F
Equation 64. COUT>ISTEP2π×VOUT×fC
Equation 65. COUT>4A2π×375mV×4kHz=424.4μF

Based on the calculations, at least 425μF of output capacitance is required. When selecting capacitors, consider any derating of capacitance that is needed to account for aging, temperature, and DC bias.

For space-grade converter designs, there is another consideration when selecting the output capacitance. This is the impact of radiation induced single event transients (SET). Single energetic particle strikes can lead to momentary variation in the PWM variation of the controller, which in turn can lead to output voltage transients in the converter. Thus, even though the value above provides a minimum value to account for voltage ripple and/or load transients, additional capacitance is likely needed for adequate SET mitigation. For the design example, approximately 470μF of total output capacitance was used.

An additional output filter can be used to further reduce the noise of the output stage if deemed necessary. This output filter consists of an additional inductor and a small amount of ceramic capacitance. The filter inductance is then located between the added ceramic capacitance and the bulk output capacitance that was determined to be required for the design. This approach can drastically reduce the output voltage ripple without significantly increasing the size and/or number of components required. The key for the secondary filter design is to choose the resonant frequency such that it is higher than the targeted crossover frequency yet well below the switching frequency and ESR zero of the bulk output capacitance. Equation 66, Equation 67, and Equation 68 can be used to determine the ESR zero as well as the resonant frequency and attenuation of the additional output filter.

Equation 66. fresonant=12π×Lf×COUT_BULK
Equation 67. fzero=12π×COUT_BULK×ESRBULK
Equation 68. Attfsw=40log10fswfresonant-20log10fswfzero

In the event that there is peaking at high frequencies due to the output filter, a resistor can be used to dampen this peaking effect. Equation 69 and Equation 70 can be used to determine the frequency of the peaking and the value of the resistor needed to provide adequate damping.

Equation 69. ωo=2×COUT_CER+COUT_BULKLf×COUT_CER×COUT_BULK
Equation 70. Rf=ROUT×Lf×COUT_CER+COUT_BULK-LfωoROUT×COUT_CER+COUT_BULKωo-Lf×COUT_CER