SLVSHI9A March   2025  – September 2025 TPS7H5020-SEP , TPS7H5020-SP

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN) and VLDO
      2. 7.3.2  Driver Input Voltage (PVIN)
      3. 7.3.3  Start-Up
      4. 7.3.4  Enable and Undervoltage Lockout (UVLO)
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Output Voltage Programming
      8. 7.3.8  Soft Start (SS)
      9. 7.3.9  Switching Frequency and External Synchronization
        1. 7.3.9.1 Internal Oscillator Mode
        2. 7.3.9.2 External Synchronization Mode
          1. 7.3.9.2.1 External Synchronization with TPS7H5021
      10. 7.3.10 Duty Cycle Limit
      11. 7.3.11 Minimum On-Time and Off-Time
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Leading Edge Blank Time
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Gate Driver Output
      16. 7.3.16 Unpowered Voltage Clamp
      17. 7.3.17 Sourcing Driver Return (OUTH_REF)
      18. 7.3.18 Slope Compensation (RSC)
      19. 7.3.19 Frequency Compensation
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistor Selection
        3. 8.2.2.3  Driver PVIN Configuration
        4. 8.2.2.4  Soft-Start Capacitor Selection
        5. 8.2.2.5  Transformer Design
        6. 8.2.2.6  Primary Power Switch Selection
        7. 8.2.2.7  Output Diode Selection
        8. 8.2.2.8  RCD Clamp
        9. 8.2.2.9  Output Capacitance Selection
        10. 8.2.2.10 Current Sense Resistor
        11. 8.2.2.11 Frequency Compensation Component Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Boost Converter
      5. 8.2.5 Feedback Isolation Using ISOS510
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

TA = –55°C to 125°C, PVIN = VIN = 4.5V to 14V, VLDO = 5V, no load on OUT (unless otherwise noted)
PARAMETER TEST CONDITIONS SUBGROUP(1) MIN TYP MAX UNIT
SUPPLY VOLTAGES AND CURRENTS
IDD Operating supply current No load for OUT, PVIN = VIN fSW = 100kHz 1, 2, 3 6.8 11 mA
fSW = 500kHz 1, 2, 3 8.5 17
IDD Operating supply current No load for OUT, PVIN = VIN fSW = 1MHz 1, 2, 3 10.3 25 mA
IDD Operating supply current CLOAD = 1000pF for OUT, PVIN = VIN fSW = 100kHz 1, 2, 3 8.5 12 mA
fSW = 500kHz 1, 2, 3 14.5 22
IDD Operating supply current CLOAD = 1000pF for OUT, PVIN = VIN fSW = 1MHz 1, 2, 3 22.5 28 mA
IDD Operating supply current CLOAD = 1000pF for OUT, VIN = 12V, PVIN = VLDO = 5V fSW = 100kHz 1, 2, 3 7 10 mA
fSW = 500kHz 1, 2, 3 10 13
fSW = 1MHz 1, 2, 3 13.5 20
Istart Startup current VIN = 3.5V 1, 2, 3 3.8 5 mA
IDD(dis) Standby current EN = 0V 1, 2, 3 8 mA
VLDO Internal linear regulator output voltage CVLDO = 1µF 5V ≤ VIN ≤ 14V, RVT = 10kΩ, RVB = 3.74kΩ  1, 2, 3 4.36 4.49 4.62 V
5.5V ≤ VIN ≤ 14V, RVT = 10kΩ, RVB = 3.24kΩ  1, 2, 3 4.84 4.99 5.14
6V ≤ VIN ≤ 14V, RVT = 10 kΩ, RVB = 2.87kΩ  1, 2, 3 5.31 5.48 5.65
VLDO_DO Internal linear dropout voltage IVLDO = 25mA, CVLDO = 1µF 1, 2, 3 0.4 V
I_VLDO Maximum VLDO output current VLDO ≥ 96% of VLDO at no load, CVLDO = 1µF VIN = VLDO + 0.5V 1, 2, 3 25(4) mA
VIN = VLDO + 1V 1, 2, 3 55(4)
VIN ≥ 7V 1, 2, 3 90(4)
ENABLE AND UNDERVOLTAGE LOCKOUT
VENR Enable rising threshold 1, 2, 3 0.57 0.63 0.66 V
VENF Enable falling threshold 1, 2, 3 0.48 0.52 0.55 V
IEN Enable input leakage current VIN = 14V EN = 1V 1, 2, 3 1 100 nA
EN = 7V 1, 2, 3 30 700 nA
PVINUVLOR PVIN UVLO rising 1, 2, 3 3.65 3.76 3.95 V
PVINUVLOF PVIN UVLO falling 1, 2, 3 3.45 3.56 3.75 V
VINUVLOR VIN UVLO rising 1, 2, 3 3.85 3.96 4.15 V
VINUVLOF VIN UVLO falling 1, 2, 3 3.65 3.76 3.95 V
VLDOUVLOR VLDO UVLO rising 1, 2, 3 3.65 3.77 3.95 V
VLDOUVLOF VLDO UVLO falling 1, 2, 3 3.45 3.59 3.75 V
SOFT START
ISS Soft-start current SS = 0.3V 1, 2, 3 2.0 2.8 3.4 µA
ERROR AMPLIFIER
EAgm Error amplifier transconductance –10µA < ICOMP < 10µA, V(COMP) = 1V 1, 2, 3 1100 1750 2700 µA/V
EADC DC gain VSENSE = 0.6V 13000 V/V
EAISRC Error amplifier source current V(COMP) = 1V, 100mV input overdrive 1, 2, 3 95 210 µA
EAISNK Error amplifier sink current V(COMP) = 1V, 100mV input overdrive 1, 2, 3 95 210 µA
EAro Error amplifier output resistance 8 MΩ
EAOS Error amplifier input offset voltage 1, 2, 3 –5 6 mV
EAIB Error amplifier input bias current 1, 2, 3 25 nA
EABW Bandwidth 1, 2, 3 7.5 MHz
OSCILLATOR
SYNCIL SYNC in low-level VLDO = 4.5V VIN < 5V 1, 2, 3 0.8 V
VIN ≥ 5V 1, 2, 3 0.8
VLDO = 5.5V VIN < 6V 1, 2, 3 0.8
VIN ≥ 6V 1, 2, 3 0.8
SYNCIH SYNC in high-level  VLDO = 4.5V VIN < 5V 1, 2, 3 3.5 V
VIN ≥ 5V 1, 2, 3 3.5
VLDO = 5.5V VIN < 6V 1, 2, 3 3.5
VIN ≥ 6V 1, 2, 3 3.5
fSYNC SYNC in frequency range 4, 5, 6 100 1000 kHz
DSYNC SYNC in duty cycle (TPS7H5020) Duty cycle of external clock 4, 5, 6 40% 60%
DSYNC SYNC in duty cycle (TPS7H5021)(5) Duty cycle of external clock, f ≥ 200kHz 4, 5, 6 48% 52%
DSYNC SYNC in duty cycle (TPS7H5021)(5) Duty cycle of external clock, 100kHz ≤ f < 200kHz Duty cycle of external clock, 100kHz ≤ f < 200kHz 4, 5, 6 49% 51%
DTINT External clock to internal clock detection time RT populated 9, 10, 11 2 5 (1/fsw) s
DTEXT Internal clock to external clock detection time RT populated 9, 10, 11 2 5 (1/fsw) s
fSW RT programmed switching frequency RT = 1.18MΩ 4, 5, 6 80 95 110 kHz
RT = 560kΩ   4, 5, 6 175 195 220
RT = 210kΩ 4, 5, 6 450 500 550
fSW RT programmed switching frequency RT = 100kΩ 4, 5, 6 925 1000 1100 kHz
VOLTAGE REFERENCE
VREF Internal voltage reference(2) Measured at COMP, COMP = VSENSE TA = 25°C 1 0.597 0.600 0.603 V
TA =  –55°C 3 0.594 0.598 0.602
TA = 125°C 2 0.597 0.601 0.604
REFCAP REFCAP voltage CREFCAP = 470nF 1, 2, 3 1.208 1.223 1.235 V
CURRENT SENSE
CCSR COMP to CS_ILIM ratio RSC = open 1, 2, 3 1.94 2.0 2.06
VCS_ILIM Current limit (overcurrent) threshold 1, 2, 3 0.96 1.0 1.04 V
CS_ILIM to OUT delay CS_ILIM = 1V to 90% of OUT falling 9, 10, 11 65 115 ns
SLOPE COMPENSATION
SC Slope compensation fSW = 100kHz, RSC = 1.18MΩ 0.029 V/µs
fSW = 200kHz, RSC = 562kΩ 0.072
fSW = 500kHz, RSC = 100kΩ 0.306
SC Slope compensation fSW = 1000kHz, RSC = 49.9kΩ 0.605 V/µs
THERMAL SHUTDOWN
TSD Thermal shutdown entry 185 °C
TSD_HYS Thermal shutdown hysteresis 15 °C
GATE DRIVER 
VOL Low-level voltage IOL = 50mA 1, 2, 3 0.08 0.15 V
PVIN - VOH High-level voltage IOH = 50mA 1, 2, 3 0.13 0.25 V
tR_OUT OUT rise time CLOAD = 1000pF, 10% to 90% VIN = PVIN = 4.5V 9, 10, 11 7 14 ns
VIN = PVIN = 5V 9, 10, 11 7 14
tR_OUT OUT rise time CLOAD = 1000pF, 10% to 90% VIN = PVIN = 12V 9, 10, 11 9.5 18 ns
VIN = PVIN = 14V 9, 10, 11 11.5 20
tR_OUT OUT rise time  CLOAD = 1000pF, 10% to 90% VIN = 12V, PVIN = VLDO 9, 10, 11 8.5 16 ns
CLOAD = 220pF, 10% to 90% 9, 10, 11 4.5 12
tF_OUT OUT fall time  CLOAD = 1000pF, 90% to 10% VIN = PVIN = 4.5V 9, 10, 11 6.5 14 ns
VIN = PVIN = 5V 9, 10, 11 6.5 14
tF_OUT OUT fall time CLOAD = 1000pF, 90% to 10% VIN = PVIN = 12V 9, 10, 11 9.5 18 ns
VIN = PVIN = 14V 9, 10, 11 11 18
tF_OUT OUT fall time  CLOAD = 1000pF, 90% to 10% VIN = 12V, PVIN = VLDO 9, 10, 11 6.5 14 ns
CLOAD = 220pF, 90% to 10% 9, 10, 11 3.5 10
IOH Peak source current  PVIN = 4.5V 1, 2, 3 0.55 A
PVIN = 5V 1, 2, 3 0.7
IOH Peak source current PVIN = 12V 1, 2, 3 1.2 A
PVIN = 14V 1, 2, 3 1.2
IOH Peak source current  VIN = 12V, PVIN = VLDO VLDO = 4.5V 1, 2, 3 0.55 A
VLDO = 5V 1, 2, 3 0.7
VLDO = 5.5V 1, 2, 3 0.85
IOL Peak sink current  PVIN = 4.5V 1, 2, 3 0.7 A
PVIN = 5V 1, 2, 3 0.8
IOL Peak sink current PVIN = 12V 1, 2, 3 1.3 A
PVIN = 14V 1, 2, 3 1.3
IOL Peak sink current  VIN = 12V, PVIN = VLDO VLDO = 4.5V 1, 2, 3 1.05 A
VLDO = 5V 1, 2, 3 1.3
VLDO = 5.5V 1, 2, 3 1.55
ROH Pull-up resistance 100mA from OUT 1, 2, 3 2.6 4.7 Ω
ROL Pull-down resistance 100mA into OUT 1, 2, 3 1.6 2.8 Ω
VUCLAMP Unpowered OUT clamp voltage Switching disabled,  1mA pull-up applied to OUT PVIN = 0V 1, 2, 3 0.7 1 V
0V < PVIN < 5V 1, 2, 3 1.8 2.5
PWM AND DUTY CYCLE
TLEB Leading edge blank time 5V ≤ VIN ≤ 14V, 10% of OUT rising to end of blanking 9, 10, 11 30 80 ns
ton_min Minimum on-time(3) 9, 10, 11 135 165 ns
toff_min Minimum off-time (TPS7H5020)(3) 9, 10, 11 55 70 ns
DMAX Maximum duty cycle (TPS7H5021)(5) 9, 10, 11 42% 46% 50%
(1) Subgroups are applicable for QML parts.  For subgroup definitions, see Section 6.6.
(2) Measured at COMP pin to include error amplifier offset.
(3) See Minimum On-Time and Off-Time for additional details.
(4) VLDO can support this current, at the least, for test conditions specified.  However, for controller operation with PVIN connected to VLDO, it is recommended to keep the external current drawn from VLDO below this value for the most reliable operation.
(5) TPS7H5021 is a product preview device.  This specification is provided for information only.