SLVSHI9A March   2025  – September 2025 TPS7H5020-SEP , TPS7H5020-SP

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Quality Conformance Inspection
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage (VIN) and VLDO
      2. 7.3.2  Driver Input Voltage (PVIN)
      3. 7.3.3  Start-Up
      4. 7.3.4  Enable and Undervoltage Lockout (UVLO)
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Output Voltage Programming
      8. 7.3.8  Soft Start (SS)
      9. 7.3.9  Switching Frequency and External Synchronization
        1. 7.3.9.1 Internal Oscillator Mode
        2. 7.3.9.2 External Synchronization Mode
          1. 7.3.9.2.1 External Synchronization with TPS7H5021
      10. 7.3.10 Duty Cycle Limit
      11. 7.3.11 Minimum On-Time and Off-Time
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Leading Edge Blank Time
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Gate Driver Output
      16. 7.3.16 Unpowered Voltage Clamp
      17. 7.3.17 Sourcing Driver Return (OUTH_REF)
      18. 7.3.18 Slope Compensation (RSC)
      19. 7.3.19 Frequency Compensation
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistor Selection
        3. 8.2.2.3  Driver PVIN Configuration
        4. 8.2.2.4  Soft-Start Capacitor Selection
        5. 8.2.2.5  Transformer Design
        6. 8.2.2.6  Primary Power Switch Selection
        7. 8.2.2.7  Output Diode Selection
        8. 8.2.2.8  RCD Clamp
        9. 8.2.2.9  Output Capacitance Selection
        10. 8.2.2.10 Current Sense Resistor
        11. 8.2.2.11 Frequency Compensation Component Selection
      3. 8.2.3 Application Curves
      4. 8.2.4 Boost Converter
      5. 8.2.5 Feedback Isolation Using ISOS510
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Frequency Compensation Component Selection

The poles and zeros of the flyback converter can be determined with the following equations. Note that the flyback converter also has a right-half-plane zero.

Equation 72. fZ_ESR=1+DMAX2π×COUT×RESR
Equation 73. fZ_ESR=1+0.352π×470μF×4m=114.3kHz
Equation 74. fP=12π×COUT×VOUTIOUT
Equation 75. fP=12π×470µF×5V4A=270.9Hz
Equation 76. fRHPZ=VOUTIOUT×(1-DMAX)22π×LPRINPS2×DMAX
Equation 77. fRHPZ=5V4A×(1-0.35)22π×30µH22×0.35=32.0kHz

Type 2A compensation network can be utilized in order to properly place the pole and zero of the error amplifier to achieve stability. Note that this compensation technique is for a flyback operating in continuous conduction mode. The crossover frequency is typically targeted to be anywhere from one-fourth of the RHP zero frequency to a full decade below. A crossover frequency of 4kHz was targeted for this design. The error amplifier network gain is set to achieve the target crossover frequency, which is dependent on RCOMP. The equation for RCOMP, as derived from Equation 21, Equation 23, and Equation 24, is shown in Equation 78. The calculation of KFB is as shown in Equation 25.

Equation 78. RCOMP=2π×fC×COUT×ACS×RCS1-DMAX×NPS×KFB×gm
Equation 79. RCOMP=2π×4kHz×470μF×1×0.1Ω1-0.35×2×0.12×1750μAV=4326.88Ω

The error amplifer zero is set to one-tenth of the crossover frequency, which allows for selecting the value of CCOMP.

Equation 80. CCOMP=12π×0.1×fC×RCOMP
Equation 81. CCOMP=12π×0.1×4kHz×4.32kΩ=91.96nF

Lastly, the high frequency pole is set to the lower of the ESR zero and the RHP zero. In this specific case, the RHP zero is lower.

Equation 82. CHF=12π×fRHPZ×RCOMP
Equation 83. CHF=12π×32kHz×4.32k=1.15nF

Using standard component values, the initial values of RCOMP, CCOMP, and CHF selected were 4.32 kΩ, 100nF, and 1nF, respectively. It is important to note that these calculated values provide a starting point. The frequency compensation is often tuned during both simulation and testing to settle on the final compensation values of the design.