SLVSHJ7A February   2025  – September 2025 DRV8163-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
    2. 5.2 SPI Variant
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Timing Diagrams
    7. 6.7 Thermal Information
      1. 6.7.1 Transient Thermal Impedance & Current Capability
    8. 6.8 Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
        2. 6.8.1.2 Low-Side Recirculation
      2. 6.8.2 Wake-up Transients
        1. 6.8.2.1 HW Variant
        2. 6.8.2.2 SPI Variant
      3. 6.8.3 Fault Reaction Transients
        1. 6.8.3.1 Retry setting
        2. 6.8.3.2 Latch setting
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Warning (OTW) - SPI Variant Only
        3. 7.3.4.3 Over Temperature Protection (TSD)
        4. 7.3.4.4 Off-State Diagnostics (OLP)
        5. 7.3.4.5 On-State Diagnostics (OLA) - SPI Variant Only
        6. 7.3.4.6 VM Over Voltage Monitor - SPI Variant Only
        7. 7.3.4.7 VM Under Voltage Monitor
        8. 7.3.4.8 Power On Reset (POR)
        9. 7.3.4.9 Event Priority
      5. 7.3.5 Device Functional Modes
        1. 7.3.5.1 SLEEP State
        2. 7.3.5.2 STANDBY State
        3. 7.3.5.3 Wake-up to STANDBY State
        4. 7.3.5.4 ACTIVE State
        5. 7.3.5.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
      6. 7.3.6 Programming - SPI Variant Only
        1. 7.3.6.1 Serial Peripheral Interface (SPI)
        2. 7.3.6.2 Standard Frame
        3. 7.3.6.3 SPI for Multiple Peripherals
          1. 7.3.6.3.1 Daisy Chain Frame for Multiple Peripherals
      7. 7.3.7 Register Map - SPI Variant Only
        1. 7.3.7.1 User Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Load Summary
    2. 8.2 Typical Application
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.7.1 User Registers

The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table is considered as "reserved" locations and access is blocked to this space.

Table 7-16 User Registers
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Type (1)
DEVICE_IDDEV_ID[5:0]REV_ID[1:0]R
FAULTERR(2)PORFAULTVMOVVMUVOCPTSDOLA(2)R
STATUS1OLA(3)OLA(3)ITRIP_CMPACTIVEOCP_H(5)OCP_L(4)OCP_H(5)OCP_L(4)R
STATUS2DRV_STATRSVD

OTW

ACTIVERSVDOLP_CMPR
COMMANDCLR_FLTRSVDSPI_IN_LOCK[1:0]RSVDREG_LOCK[1:0]R/W
SPI_INRSVDS_DRVOFFRSVDRSVDS_INR/W
CONFIG1EN_OLAOTW_SEL

OVSEL

SSC_DISOCP_RTRYTSD_RTRYOV_RTRYOLA_RTRYR/W
CONFIG2RSVDS_DIAG[1:0]

ISEL[1:0]

S_ITRIP[2:0]R/W
CONFIG3TOFF[1:0]RSVDTBLK

SR[1:0]

RSVDR/W
CONFIG4

OTW_REP

TOCP

OLA_FLTR

OCP_SEL[1:0]DRV_SELRSVDIN_SELR/W
(1) R = Read Only, R/W = Read/Write
(2) OLA replaced by ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
(3) OLA is indicated if either of the two OLA bits is set
(4) OCP_L is indicated if either of the two OCP_L bits is set
(5) OCP_H is indicated if either of the two OCP_H bits is set

3.7.1.1 DEVICE_ID register (Address = 00h)

Return to the User Register table.

DeviceDEVICE_ID value
DRV8163S-Q10 x 2C

3.7.1.2 FAULT Register (Address = 01h) [reset = 40h]

Return to the User Register table.

BitFieldTypeResetDescription
7ERRR0b1b indicates that a SPI communication fault has occurred in the previous SPI frame.
6PORR1b1b indicates that a power-on-reset has been detected.
5FAULTR0bLogic OR of ERR, POR, VMUV, OCP & TSD
4

VMOV

R0b1b indicates that a VM over voltage has been detected.
3VMUVR0b1b indicates that a VM under voltage has been detected.
2OCPR0b1b indicates that an over current has been detected in either one or more power FETs. Refer OCP_SEL, TOCP to change thresholds & filter times. Refer OCP_RETRY to configure fault reaction.
1TSDR0b1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure fault reaction.
0OLAR0b1b indicates that an open load condition has been detected in the ACTIVE state. Refer to EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.

3.7.1.3 STATUS1 Register (Address = 02h) [reset = 00h]

Return to the User Register table.

BitFieldTypeResetDescription
7OLAR0b1b indicates that an open load condition has been detected in the ACTIVE state on OUT
6OLAR0b1b indicates that an open load condition has been detected in the ACTIVE state on OUT
5ITRIP_CMPR0b1b indicates that load current has reached the ITRIP regulation level.
4ACTIVER0b1b indicates that the device is in the ACTIVE state
3OCP_HR0b1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT
2OCP_LR0b1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT
1OCP_HR0b1b indicates that an over current has been detected on the high-side FET (short to GND) on OUT
0OCP_LR0b1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT

3.7.1.4 STATUS2 Register (Address = 03h) [reset = 0h]

Return to the User Register table.

BitFieldTypeResetDescription
7DRV_STATR-

This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.

6RSVDR0bReserved

5

OTW

R

0b

1b indicates that a over temperature warning event has been detected.

4ACTIVER0b1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
3-1RSVDR000bReserved
0OLP_CMPR0bThis bit is the output of the off-state diagnostics (OLP) comparator.

3.7.1.5 COMMAND Register (Address = 08h) [reset = 09h]

Return to the User Register table.

BitFieldTypeResetDescription
7CLR_FLTR/W0bClear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert the nFAULT pin
6-5RSVDR00bReserved
4-3SPI_IN_LOCKR/W01b

  • Write 10b to unlock the SPI_IN register

  • Write 01b or 00b or 11b to lock the SPI_IN register

  • SPI_IN register is locked by default.

2RSVDR0bReserved
1-0REG_LOCKR/W01b

  • Write 10b to lock the CONFIG registers

  • Write 01b or 00b or 11b to unlock the CONFIG registers

  • CONFIG registers are unlocked by default.

3.7.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]

Return to the User Register table.

BitFieldTypeResetDescription
7-4RSVDR0000bReserved
3S_DRVOFFR/W1bRegister bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control section.
2-1RSVDR10bReserved
0S_INR/W0bRegister bit equivalent of IN pin when SPI_IN is unlocked. Refer Register Pin control section

3.7.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]

Return to the User Register table.

BitFieldTypeResetDescription
7EN_OLAR/W0bWrite 1b to enable open load detection in the active state. In Independent mode, OLA is always disabled for low-side load. Refer DIAG section.
6OTW_SELR/W0bOver Temperature Warning threshold

0b = 140 °C

1b = 120 °C

5

OVSEL

R/W

0b

0b: VMOV enabled

1b: VMOV disabled

4SSC_DISR/W1b0b: Enables the spread spectrum clocking feature
3OCP_RTRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of over current, else the fault reaction is latched
2TSD_RTRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of over temperature, else the fault reaction is latched
1OV_RTRYR/W0b

Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault reaction is latched. This bit also controls the fault reaction for a VM under voltage detection.

0OLA_RTRYR/W0bWrite 1b to configure fault reaction to retry setting on the detection of open load during active, else the fault reaction is latched.

3.7.1.8 CONFIG2 Register (Address = 0Bh) [reset = 18h]

Return to the User Register table.

BitFieldTypeResetDescription
7RSVDR0bReserved
6-5S_DIAGR/W00bLoad type indication - refer to DIAG table

4-3

ISEL

R/W

11b

Selects between proportional current output and Die temperature readout voltage.
2-0S_ITRIPR/W000bITRIP level configuration - refer ITRIP table

3.7.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]

Return to the User Register table.

BitFieldTypeResetDescription
7-6TOFFR/W01bTOFF time used for ITRIP current regulation

00b = 20 µsec

01b = 30 µsec

10b = 40 µsec

11b = 50 µsec

5

RSVD

R

1b

Reserved.

4

TBLK

R/W

0b

Blanking time configuration

0b = 2.4 µsec

1b = 3.4 µsec

3-2SRR/W00bSlew Rate configuration

00b = 155V/µs

01b = 83V/µs

10b = 39V/µs
11b = 16V/µs
1-0RSVDR10bReserved

3.7.1.10 CONFIG4 Register (Address = 0Dh) [reset = 44h]

Return to the User Register table.

BitFieldTypeResetDescription

7

OTW_REP

R/W

0b

0b = Over temperature warning is not reported on nFAULT

1b = Over temperature warning is reported on nFAULT

6TOCPR/W1bFilter time for over current detection configuration

0b = 1 µsec

1b = 2 µsec

5

OLA_FLTR

R/W0bSelects OLA filter count. 0b = 16 count, 1b = 1024 count.
4-3OCP_SELR/W00bThreshold for over current detection configuration
2DRV_SELR/W1bDRVOFF pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND

1RSVDR/W0bReserved
0IN_SELR/W0bIN pin - register logic combination, when SPI_IN is unlocked

0b = OR

1b = AND

3.7.1.11 CONFIG6 Register (Address = 10h) [reset = 00h]

DRV8163A-Q1 additional configuration options. Return to the User Register table.

Bit Field Type Reset Description

7

 PU1_EN R/W 0b Manual Off-sate diagnostics: High-side ROLP_PU enable, overrides pin controlled OLP based on OLP_CMP_SEL = 00b configuration. Retains value until S_DRVOFFx for selected output is set to 0.

0b = Disable

1b = Enable
6 PD1_EN R/W 0b Manual Off-sate diagnostics: Low-side ROLP_PD enable, overrides pin controlled OLP based on OLP_CMP_SEL = 00b configuration. Retains value until S_DRVOFFx for selected output is set to 0.

0b = Disable

1b = Enable
5 RHIZ1_DIS R/W 0b Manual Off-sate diagnostics: RHIZ1 disable, overrides pin controlled OLP based on OLP_CMP_SEL = 00b configuration.

0b = Enable

1b = Disable
4-2 RSVD R 000b Reserved
1 M_OLP_EN R/W 0b Manual Off-sate diagnostics enable: overrides pin controlled OLP selection and is enabled for selected output on OLP_CMP_SEL.

0b = Disable

1b = Enable
0 CMP_REF_SEL R/W 0b Manual Off-sate diagnostics: comparator reference select, overrides pin controlled OLP_CMP_SEL selection and outputs result on OLP_CMP status bit.

0b = VOLP_REFL

1b = VOLP_REFH