SLVSHJ7A February   2025  – September 2025 DRV8163-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
    2. 5.2 SPI Variant
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 Timing Diagrams
    7. 6.7 Thermal Information
      1. 6.7.1 Transient Thermal Impedance & Current Capability
    8. 6.8 Switching Waveforms
      1. 6.8.1 Output switching transients
        1. 6.8.1.1 High-Side Recirculation
        2. 6.8.1.2 Low-Side Recirculation
      2. 6.8.2 Wake-up Transients
        1. 6.8.2.1 HW Variant
        2. 6.8.2.2 SPI Variant
      3. 6.8.3 Fault Reaction Transients
        1. 6.8.3.1 Retry setting
        2. 6.8.3.2 Latch setting
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Warning (OTW) - SPI Variant Only
        3. 7.3.4.3 Over Temperature Protection (TSD)
        4. 7.3.4.4 Off-State Diagnostics (OLP)
        5. 7.3.4.5 On-State Diagnostics (OLA) - SPI Variant Only
        6. 7.3.4.6 VM Over Voltage Monitor - SPI Variant Only
        7. 7.3.4.7 VM Under Voltage Monitor
        8. 7.3.4.8 Power On Reset (POR)
        9. 7.3.4.9 Event Priority
      5. 7.3.5 Device Functional Modes
        1. 7.3.5.1 SLEEP State
        2. 7.3.5.2 STANDBY State
        3. 7.3.5.3 Wake-up to STANDBY State
        4. 7.3.5.4 ACTIVE State
        5. 7.3.5.5 nSLEEP Reset Pulse (HW Variant, LATCHED setting Only)
      6. 7.3.6 Programming - SPI Variant Only
        1. 7.3.6.1 Serial Peripheral Interface (SPI)
        2. 7.3.6.2 Standard Frame
        3. 7.3.6.3 SPI for Multiple Peripherals
          1. 7.3.6.3.1 Daisy Chain Frame for Multiple Peripherals
      7. 7.3.7 Register Map - SPI Variant Only
        1. 7.3.7.1 User Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Load Summary
    2. 8.2 Typical Application
      1. 8.2.1 HW Variant
      2. 8.2.2 SPI Variant
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.4 Electrical Characteristics

4.5 V ≤ VVM ≤ 65 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, VDD)
IVDD VDD current in ACTIVE state Die temperature readout disabled 2 3.5 mA
IVMS VM current in STANDBY state VVM = 48 V, Drivers Hi-Z, Die temperature readout disabled 1 1.8 mA
IVMQ VM current in SLEEP state VVM = 48 V, VnSLEEP = 0 V or VVDD < PORVDD_FALL 7 30 µA
tRESET RESET pulse filter time Reset signal on nSLEEP, HW variant 5 35 µs
tSLEEP Sleep command filter time Sleep signal on nSLEEP, HW variant 40 120 µs
tSLEEP_SPI Sleep command filter time Sleep signal on nSLEEP, SPI variant 5 20 µs
tCOM Time for communication to be available after wake-up or power-up through VM or VDD pin Wake-up signal on nSLEEP pin or power cycle (VVM > VMPOR_RISE or VVDD > VDDPOR_RISE) 0.2 ms
tREADY Time for driver ready to be driven after wake-up through nSLEEP or power-up through VM or VDD Wake-up signal on nSLEEP pin or power cycle (VVM > VMPOR_RISE or VVDD > VDDPOR_RISE) 1.2 ms
CONTROLLER (nSLEEP, DRVOFF, EN/IN1, PH/IN2, IN) and SPI INPUTS (SDI, nSCS, SCLK)
VIL Input logic low voltage All pins 0 0.6 V
VIH Input logic high voltage All pins 1.5 5.5 V
VHYS Input hysteresis All pins except nSLEEP 0.1 V
VHYS_nSLEEP Input hysteresis on nSLEEP pin 0.15 V
RPU Internal pull-up resistance on DRVOFF and nSCS Measured at min VIH level 150 450 kΩ
RPD Input pull-down resistance on IN, SDI, SCLK Measured at max VIL level 150 450 kΩ
RPD_nSLEEP Input pull-down resistance on nSLEEP to GND Measured at max VIL level 160 400 kΩ
TRI-LEVEL INPUT (MODE)
RLVL1 Level 1 Connect to GND 10 Ω
RLVL2 Level 2 +/- 10% resistor to GND 8 16 24 kΩ
RLVL3 Level 3 Hi-Z (no connect) 249 kΩ
Quad-level Input (SR)
RLVL1 Level 1 Connect to GND 10 Ω
RLVL2 Level 2 +/-10% resistor GND 8 16 24 kΩ
RLVL3 Level 3 +/-10% resistor GND 45 75 110 kΩ
RLVL4 Level 4 Hi-Z (no connect) 249 kΩ
6 LEVEL INPUT (ITRIP, DIAG)
RLVL1 Level 1 Connect to GND 10 Ω
RLVL2 Level 2 +/- 10% resistors 8 9 10 kΩ
RLVL3 Level 3 +/- 10% resistors 22 24 26 kΩ
RLVL4 Level 4 +/- 10% resistors 45 48 51 kΩ
RLVL5 Level 5 +/- 10% resistors 90 100 110 kΩ
RLVL6 Level 6 Hi-Z (no connect) 249 kΩ
PUSH-PULL and Control Outputs (SDO, nFAULT)
VOL_SDO SDO Output logic-low voltage 0.5 mA sink 0.1 0.2 V
VOH_SDO SDO Output logic-high voltage 0.5 mA source, VVDD = 5 V 4.7 4.9 V
ISDO SDO Leakage Current VVM > 6 V -2 2 µA
VOL nFAULT Output logic-low voltage IO = 5 mA 0.3 V
IOH nFAULT Output logic-high leakage -1 1 µA
DRIVER OUTPUT (OUTx)
RHS_DS(on) High-side MOSFET on resistance, DRV8163 IO = -6 A, TJ = 25°C 21 25 mΩ
RHS_DS(on) High-side MOSFET on resistance, DRV8163 IO = -6 A, TJ = 150°C 35 42 mΩ
RLS_DS(on) Low-side MOSFET on resistance, DRV8163 IO = 6 A, TJ = 25°C 22 26 mΩ
RLS_DS(on) Low-side MOSFET on resistance, DRV8163 IO = 6 A, TJ = 150°C 36 43 mΩ
VSD Body diode forward voltage IO = -4 A (8263), -6A (8163) 0.4 0.8 1.2 V
IHIZ_SLP OUTx leakage current to GND in SLEEP state V(OUTx) = VM = 48 V, per OUT pin 140 µA
IHIZ_STBY OUTx leakage current to GND in Standby state V(OUTx) = VM = 48 V, per OUT pin 1 21 mA
SRLS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 00b or LVL1, high-side recirculation 146 192 237 V/µs
SRLS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 00b or LVL1, high-side recirculation 130 160 204 V/µs
SRLS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 01b or LVL2, high-side recirculation 73 99 124 V/µs
SRLS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 01b or LVL2, high-side recirculation 67 83 107 V/µs
SRLS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 10b or LVL3, high-side recirculation 32 46 60 V/µs
SRLS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 10b or LVL3, high-side recirculation 26 38 52 V/µs
SRLS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 11b or LVL4, high-side recirculation 11 18 25 V/µs
SRLS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 11b or LVL4, high-side recirculation 8 14.5 21.5 V/µs
tPD_LSOFF Propagation delay during output voltage rise SR = 00b or 01b or LVL1 or LVL2, high-side recirculation 0.3 µs
tPD_LSOFF Propagation delay during output voltage rise SR = 10b or 11b or LVL3 or LVL4, high-side recirculation 0.5 µs
tPD_LSON Propagation delay during output voltage fall SR = 00b or 01b or LVL1 or LVL2, high-side recirculation 0.26 µs
tPD_LSON Propagation delay during output voltage fall SR = 10b or 11b or LVL3 or LVL4, high-side recirculation 0.33 µs
tDEAD_LSOFF Dead time during output voltage rise SR = 00b or 01b or LVL1 or LVL2, high-side recirculation 0.95 µs
tDEAD_LSOFF Dead time during output voltage rise SR = 10b or LVL3, high-side recirculation 0.83 µs
tDEAD_LSOFF Dead time during output voltage rise SR = 11b or LVL4, high-side recirculation 1.06 µs
tDEAD_LSON Dead time during output voltage fall SR = 00b or 01b or LVL1 or LVL2, high-side recirculation 0.5 µs
tDEAD_LSON Dead time during output voltage fall SR = 10b or LVL3, high-side recirculation 0.53 µs
tDEAD_LSON Dead time during output voltage fall SR = 11b or LVL4, high-side recirculation 0.62 µs
SRHS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 00b or LVL1, low-side recirculation 89 130 185 V/µs
SRHS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 00b or LVL1, low-side recirculation 140 180 230 V/µs
SRHS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 01b or LVL2, low-side recirculation 50 71 98 V/µs
SRHS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 01b or LVL2, low-side recirculation 70 94 122 V/µs
SRHS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 10b or LVL3, low-side recirculation 23 33 47 V/µs
SRHS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 10b or LVL3, low-side recirculation 31 45 59 V/µs
SRHS Output voltage rise slew rate, 10% - 90%, VVM = 48 V SR = 11b (SPI only), low-side recirculation 7 13 21 V/µs
SRHS Output voltage fall slew rate, 90% - 10%, VVM = 48 V SR = 11b (SPI only), low-side recirculation 13 19 26 V/µs
tPD_HSON Propagation delay during output voltage rise SR = 00b or 01b or LVL1 or LVL2, low-side recirculation 0.35 µs
tPD_HSON Propagation delay during output voltage rise SR = 10b or 11b or LVL3 or LVL4, low-side recirculation 0.68 µs
tPD_HSOFF Propagation delay during output voltage fall SR = 00b or 01b or LVL1 or LVL2, low-side recirculation 0.27 µs
tPD_HSOFF Propagation delay during output voltage fall SR = 10b or LVL3, low-side recirculation 0.33 µs
tPD_HSOFF Propagation delay during output voltage fall SR = 11b or LVL4, low-side recirculation 0.38 µs
tDEAD_HSON
Dead time during output voltage rise

 SR = 00b or LVL1, low-side recirculation 0.46 µs
tDEAD_HSON
Dead time during output voltage rise

 SR = 01b or LVL2, low-side recirculation 0.52 µs
tDEAD_HSON
Dead time during output voltage rise

 SR = 10b or LVL3, low-side recirculation 0.60 µs
tDEAD_HSON
Dead time during output voltage rise

 SR = 11b or LVL4, low-side recirculation 0.60 µs
tDEAD_HSOFF Dead time during output voltage fall All SRs, low-side recirculation 0.1 µs
tBLANK Current regulation blanking time (Valid for only for LS recirculation) TBLK = 0b. Only choice for HW. 2.4 µs
tBLANK Current regulation blanking time (Valid for only for LS recirculation) TBLK = 1b 3.4 µs
CURRENT SENSE AND REGULATION (IPROPI, VREF)
AIPROPI Current mirror gain 202 µA/A
AERR Current mirror scaling error IOUT > 2 A -4 4 %
AERR Current mirror scaling error 0.5 A < IOUT ≤ 2 A –10 10 %
AERR Current mirror scaling error 0.2 A < IOUT ≤ 0.5 A –25 25 %
AERR_M Current matching between the two half-bridges IOUT > 2 A –3 3 %
VIPROPI_LIM Internal clamping voltage on IPROPI 3.4 5.5 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 001b or LVL2 1.08 1.2 1.3 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 010b (SPI only) 1.31 1.44 1.55 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 011b (SPI only) 1.53 1.67 1.81 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 100b or LVL3 1.83 2 2.16 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 101b or LVL4 2.14 2.34 2.52 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 110b or LVL5 2.44 2.67 2.88 V
VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation S_ITRIP = 111b or LVL6 2.74 3 3.24 V
tOFF ITRIP regulation off-time TOFF = 00b 9 20 35 µs
tOFF ITRIP regulation off-time TOFF = 01b. Only choice for HW. 15 30 45 µs
tOFF ITRIP regulation off-time TOFF = 10b 20 40 60 µs
tOFF ITRIP regulation off-time TOFF = 11b 25 50 70 µs
PROTECTION CIRCUITS
VVMOV VM over voltage threshold while rising OVSEL = 0b (SPI only) 59.5 64.5 V
VVMOV_HYS
VM over voltage hysteresis

 0.7 V
tVMOV
VM over voltage deglitch time

 4 12 19 µs
VVMUV VM Under Voltage VM falling 4.1 4.25 4.4 V
VVMUV VM Under Voltage VM rising 4.15 4.3 4.45 V
VVMUV_HYS VM UV hysteresis Rising to falling threshold 0.065 V
tVMUV VM UV deglitch time 3 12 20 µs
VPOR_FALL VDD voltage at which device goes into POR
 		 2.7 V
VPOR_RISE VDD voltage at which device comes out of POR
 		 2.8 V
IOCP Overcurrent protection threshold, DRV8163 OCP_SEL = 11b, only choice for HW 56 94 A
IOCP Overcurrent protection threshold, DRV8163 OCP_SEL = 10b 44 75 A
IOCP Overcurrent protection threshold, DRV8163 OCP_SEL = 01b 29 52 A
IOCP Overcurrent protection threshold, DRV8163 OCP_SEL = 00b 15 29.5 A
tOCP Overcurrent protection deglitch time TOCP = 0b 0.5 1 1.65 µs
tOCP Overcurrent protection deglitch time TOCP = 1b, only choice for HW 0.6 2 3.5 µs
tRETRY Overcurrent protection retry time Fault reaction set to RETRY 2.6 5 6.7 ms
tCLEAR Fault free operation time to auto-clear from over current event Fault reaction set to RETRY 70 140 µs
TTSD Thermal shutdown temperature Die temperature TJ 155 170 185 °C
THYS Thermal shutdown hysteresis Die temperature TJ 20 °C
tTSD Thermal shutdown deglitch time 7 12 18 µs
tCLEAR_TSD Fault free operation time to auto-clear from over temperature event Fault reaction set to RETRY 3.6 5 6.4 ms
TOTW Over temperature warning threshold Die temperature TJ, OTW_SEL = 0b 125 140 155 °C
TOTW Over temperature warning threshold Die temperature TJ, OTW_SEL = 1b 105 120 135 °C
THYS_OTW Over temperature warning hysteresis Die temperature TJ 20 °C
tOTW Over temperature warning deglitch time 7 12 18 µs
TDIE Die temperature measurement range Die temperature TJ -40 185 °C
IIPROPI_DIE IPROPI current range for die temperature measurement 0.5 1.5 mA
TDIE_ACC Die temperature measurement accuracy Error relative to ideal IPROPI current -10 10 %
ROPEN_LS_High Output resistance range detected as open OUTx-GND resistance, low side load 1 ∞ kΩ
ROPEN_LS_X Output resistance range with indeterminate detection (may be detected as either state) OUTx-GND resistance, low side load 0.4 1 kΩ
ROPEN_LS_Low Output resistance range detected as normal OUTx-GND resistance, low side load 0 0.4 kΩ
ROPEN_HS_High Output resistance range detected as open OUTx-VM resistance, high side load, VVM = 48 V 13 ∞ kΩ
ROPEN_HS_X Output resistance range with indeterminate detection (may be detected as either state) OUTx-VM resistance, high side load, VVM = 48 V 6.5 13 kΩ
ROPEN_HS_Low Output resistance range detected as normal OUTx-VM resistance, high side load, VVM = 48 V 0 6.5 kΩ
VOLP_REFH OLP Comparator Reference High 2.7 V
VOLP_REFL OLP Comparator Reference Low 2.2 V
ROLP_PU Internal pull-up resistance on OUT to internal 5V during OLP VOUTx = VOLP_REFH + 0.1 V 0.5 kΩ
ROLP_PD Internal pull-down resistance on OUT to GND during OLP VOUTx = VOLP_REFL - 0.1 V 0.5 kΩ
IPD_OLA Internal sink current on OUTx to GND during dead-time in high-side recirculation, 220 V/us slew rate 10 24 mA
IPD_OLA Internal sink current on OUTx to GND during dead-time in high-side recirculation, 110V/us slew rate 5 12 mA
IPD_OLA Internal sink current on OUTx to GND during dead-time in high-side recirculation, 50V/us slew rate 2.3 6 mA
IPD_OLA Internal sink current on OUTx to GND during dead-time in high-side recirculation, 20V/us slew rate 0.8 2.6 mA
VOLA_REF Comparator Reference with respect to VM used for OLA 0.28 V