SLVSHX5A
July 2025 – December 2025
TPS2HC08-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
SNS Timing Characteristics
6.7
Switching Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Accurate Current Sense
8.3.1.1
SNS Response Time
8.3.1.2
SNS Output Filter
8.3.1.3
Multiplexing of Current Sense Across Channels
8.3.1.4
Multiplexing of Current Sense Across Devices
8.3.2
Overcurrent Protection
8.3.2.1
Adjustable Current Limit
8.3.2.1.1
Current Limiting With Thermal Regulation
8.3.2.1.2
Current Limiting With No Thermal Regulation
8.3.2.1.3
Current Limit Foldback
8.3.2.1.4
Current Limit Accuracy
8.3.2.2
Thermal Shutdown
8.3.2.2.1
Relative Thermal Shutdown
8.3.2.2.2
Absolute Thermal Shutdown
8.3.3
Retry Protection Mechanism From Thermal Shutdown
8.3.3.1
Reliable Switch-On Behavior
8.3.4
Inductive-Load Switching-Off Clamp
8.3.5
Slower Slew Rate Option
8.3.6
Capacitive Load Charging
8.3.6.1
Adjustable Current Limiting for Inrush Control
8.3.6.2
Current Limit with Thermal Regulation for Capacitive Loads
8.3.6.3
Retry Thermal Shutdown Behavior for Capacitive Loads
8.3.6.4
Impact of DC Load on Capacitive Charging Capability
8.3.6.5
Device Capability
8.3.7
Bulb Charging
8.3.7.1
Non-Thermal Regulated Mode for Bulb Loads
8.3.7.2
Thermal Management During Bulb Inrush
8.3.7.3
Device Capability
8.3.8
Fault Detection and Reporting
8.3.8.1
Diagnostic Enable Function
8.3.8.2
FLT Reporting
8.3.8.3
FLT Timings
8.3.8.4
Fault Table
8.3.9
Full Diagnostics
8.3.9.1
Open-Load Detection
8.3.9.1.1
Channel On
8.3.9.1.2
Channel Off
8.3.9.2
Short-to-Battery Detection
8.3.9.3
Reverse-Polarity and Battery Protection
8.3.10
Full Protections
8.3.10.1
UVLO Protection
8.3.10.2
Loss of GND Protection
8.3.10.3
Loss of Power Supply Protection
8.3.10.4
Reverse Current Protection
8.3.10.5
Protection for MCU I/Os
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
EMC Transient Disturbances Test
9.2.3
Transient Thermal Performance
9.2.4
Application Curves
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Examples
9.4.2.1
Without a GND Network
9.4.2.2
With a GND Network
9.4.3
Wettable Flank Package
10
Device and Documentation Support
10.1
Third-Party Products Disclaimer
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
6.8
Typical Characteristics
Figure 6-1
Standby Current (I
SLEEP
) vs Temperature
Figure 6-3
Output Leakage Current (I
OUT(SLEEP)
) vs Temperature for Channel 1
Figure 6-5
On-resistance (R
ON
) vs VBB for Channel 1
Figure 6-7
I
SNS
leakage with Diagnostics disabled vs Temperature
Figure 6-9
Channel Turn-on Delay Time (t
DR
) vs Temperature for Channel 1
Figure 6-11
Channel Turn-off Delay Time (t
DF
) vs Temperature for Channel 1
Figure 6-13
VOUT Rising Slew Rate (SR
R
) vs Temperature for Channel 1 (P version)
Figure 6-15
VOUT Falling Slew Rate (SR
F
) vs Temperature for Channel 1 (P version)
Figure 6-17
Channel Turn-on Time (t
ON
) vs Temperature for Channel 1
Figure 6-19
Channel Turn-off Time (t
OFF
) vs Temperature for Channel 1
Figure 6-21
DIAG_EN Input Voltage High Level vs Temperature
Figure 6-23
DIAG_EN Input Voltage Hysteresis vs Temperature
Figure 6-25
DIAG_EN Input Current High Level vs Temperature
Figure 6-27
Open-Load Detection Voltage (V
OL
) vs Temperature for Channel 2
Figure 6-29
Current Limit Regulation Level (I
CL
) vs VBB for Channel 2, R
LIM
= OPEN
Figure 6-31
Current Limit Regulation Level (I
CL
) vs VBB for Channel 2, R
LIM
= 40kΩ
Figure 6-33
Undervoltage Lockout Thresholds (V
UVLOR
, V
UVLOF
) vs Temperature
Figure 6-2
Quiescent Current (I
Q)
) vs Temperature with Both Channels Enabled
Figure 6-4
Output Leakage Current (I
OUT(SLEEP)
) vs Temperature for Channel 2
Figure 6-6
On-resistance (R
ON
) vs VBB for Channel 2
Figure 6-8
I
SNS
fault high-level current vs Temperature
Figure 6-10
Channel Turn-on Delay Time (t
DR
) vs Temperature for Channel 2
Figure 6-12
Channel Turn-off Delay Time (t
DF
) vs Temperature for Channel 2
Figure 6-14
VOUT Rising Slew Rate (SR
R
) vs Temperature for Channel 2 (P version)
Figure 6-16
VOUT Falling Slew Rate (SR
F
) vs Temperature for Channel 2 (P version)
Figure 6-18
Channel Turn-on Time (t
ON
) vs Temperature for Channel 2
Figure 6-20
Channel Turn-off Time (t
OFF
) vs Temperature for Channel 2
Figure 6-22
DIAG_EN Input Voltage Low Level vs Temperature
Figure 6-24
DIAG_EN Input Current Low Level vs Temperature
Figure 6-26
Open-Load Detection Voltage (V
OL
) vs Temperature for Channel 1
Figure 6-28
Current Limit Regulation Level (I
CL
) vs VBB for Channel 1, R
LIM
= OPEN
Figure 6-30
Current Limit Regulation Level (I
CL
) vs VBB for Channel 1, R
LIM
= 40kΩ
Figure 6-32
Current Limit Derating factor (I
CL_HV
) vs VBB for both channels, R
LIM
= GND