Open load detection is available in the off state if DIAG_EN = Logic High. If a channel is off and a load is connected to the channel, the output voltage is pulled low to ≅0V by the load. In the case of an open load on the channel, the output voltage is close to the supply voltage, VBB – V_OUTx < V_OL. The FLT pin goes low to indicate a fault to the MCU. If the particular channel experiencing the open load fault is selected through the SEL pin, then the SNS pin outputs I_SNSFH fault current. If the channel is not selected through the SEL pin then the SNS pin does not show I_SNSFH until the channel is selected through the SEL pin. There is always a leakage current I_OL,OFF present on the output, due to the internal logic control path or external humidity, corrosion, and so forth. Thus, the device implements an internal pullup resistor (R_PU) on each channel to offset the leakage current. This pullup current must be less than the output load current to avoid false detection in the normal operation mode. To reduce the standby current, the device implements a switch and pullup resistor on each channel which is controlled by the DIAG_EN pin and the EN pin for that channel.

There are two settings for the open-load detection delay - 0.4ms (for P and D variants) and 2.4ms (for M and B variants). The 2.4ms open load detection delay represents the delay for the internal pullup (R_PU) resistor to engage between VBB and V_OUTx pins. This allows user to do fast DIAG_EN sequencing (DIAG_EN high pulse < 2.4ms) when SNS pins of multiple devices are tied to common R_SNS for MCU current sense reading. In this case, the open load fault will not engage for disabled devices during current sense read.

Figure 8-37 Open-Load Detection in Off-State

Note:

Rise and fall times of control signals are 100ns. Control signals include: ENx, DIAG_EN and SEL.

Both the channels have same open-load detection timings with appropriate SEL setting.

Figure 8-38 Open-load Detection Timing Characteristics