SNAU297 July   2025 LMK5B12212 , LMK5C22212A

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Using LMK5B12212EVM to evaluate LMK5C22212A
  6. 2Hardware
    1. 2.1 Test Equipment Recommended
    2. 2.2 LMK5B12212EVM Default Settings
    3. 2.3 EVM Quick Start
  7. 3Software
    1. 3.1 Getting Started With TICS Pro
    2. 3.2 Programming the LMK5B12212
    3. 3.3 Configuring TICS Pro
      1. 3.3.1  Using the Start Page
        1. 3.3.1.1 Step 1
        2. 3.3.1.2 Step 2
        3. 3.3.1.3 Step 3
        4. 3.3.1.4 Step 4
        5. 3.3.1.5 Step 5
        6. 3.3.1.6 Step 6
        7. 3.3.1.7 Step 7
        8. 3.3.1.8 Step 8
      2. 3.3.2  Using the Status Page
      3. 3.3.3  Using the Input Page
        1. 3.3.3.1 Cascaded Configurations
          1. 3.3.3.1.1 Cascade VCO to APLL Reference
      4. 3.3.4  Using APLLx Pages
        1. 3.3.4.1 APLL DCO
      5. 3.3.5  Using the DPLLx Page
        1. 3.3.5.1 DPLL DCO
      6. 3.3.6  Using the Validation Page
      7. 3.3.7  Using the GPIO Page
        1. 3.3.7.1 SYNC/SYSREF/1-PPS Page
      8. 3.3.8  Using the Outputs Page
      9. 3.3.9  EEPROM Page
      10. 3.3.10 Design Report Page
  8. 4EVM Configuration
    1. 4.1 Evaluation Setup
      1. 4.1.1 Power Supply
      2. 4.1.2 Logic Inputs and Outputs
      3. 4.1.3 Switching Between I2C and SPI
      4. 4.1.4 Generating SYSREF Request
      5. 4.1.5 XO Input
        1. 4.1.5.1 48MHz TCXO (Default)
        2. 4.1.5.2 External Clock Input
        3. 4.1.5.3 Additional XO Input Options
        4. 4.1.5.4 APLL Reference Options
      6. 4.1.6 Reference Clock Inputs
      7. 4.1.7 Clock Outputs
      8. 4.1.8 Status Outputs and LEDS
      9. 4.1.9 Requirements for Making Measurements
    2. 4.2 Typical Phase Noise Characteristics
  9. 5Hardware Design Files
    1. 5.1 Schematics
      1. 5.1.1  Power Supply Schematic
      2. 5.1.2  Alternative Power Supply Schematic
      3. 5.1.3  Power Distribution Schematic
      4. 5.1.4  LMK5B12212 and Input References IN0 to IN1 Schematic
      5. 5.1.5  Clock Outputs OUT0 to OUT3 Schematic
      6. 5.1.6  Clock Outputs OUT4 to OUT7 Schematic
      7. 5.1.7  Clock Outputs OUT8 to OUT11 Schematic
      8. 5.1.8  XO Schematic
      9. 5.1.9  Logic I/O Interfaces Schematic
      10. 5.1.10 USB2ANY Schematic
    2. 5.2 PCB Layouts
      1. 5.2.1 Layout Guidelines
      2. 5.2.2 Layout Example
      3. 5.2.3 Thermal Reliability
    3. 5.3 Bill of Materials (BOM)
      1. 5.3.1 Loop Filter and Vibration Nonsensitive Capacitors

4.1.1 Power Supply

The LMK5B12212 has VDD and VDDO supply pins that operate from 3.3V ± 5%.

J500 is the main power terminal to the external power supply. Power SMA port VIN1 (J2) provides an alternative connector style to apply power through coax cable. By default this SMA connector is not populated.

On the EVM, there are three methods for supplying power.

  1. The default power configuration uses the onboard DC/DC supply (U500) to power all VDD and VDDO pins as well as the onboard XO from an external 12V supply input to VIN4 on J500.
  2. The LDO power configuration uses three separate LDO regulators (U9, U10, and U11) to power the VDD, VDDO, and XO from an external 5V supply input to VIN1 on J500 (or J2).
  3. The direct power configuration allows for separate voltage supplies for the VDD, VDDO, and XO. In the direct power configuration mode, an external 3.3V supply is provided to VIN1 to power the VDD pins, an external 3.3V supply is provided to VIN2 to power the VDDO pins, and an external 3.3V supply is provided to VIN3 to power the onboard XO.
Note: Not every power connection is used or required to operate the EVM. Other power configurations are possible. See the power schematics in Figure 5-1 and Figure 5-3.
LMK5B12212EVM Default Power Jumper Configuration Figure 4-2 Default Power Jumper Configuration

Figure 4-2 shows the default power jumper locations and settings. Table 4-2 shows the suggested power configurations for the LMK5B12212

Table 4-2 Suggested Power Configurations
CONNECTIONNAME

ONBOARD DC/DC SUPPLY (DEFAULT)

ONBOARD LDO REGULATORSDIRECT EXTERNAL SUPPLIES

VDD = 3.3V (DCDC)

VDDO = 3.3V (DCDC)

XO = 3.3V (DCDC)

VDD = 3.3V (LDO1)

VDDO = 3.3V (LDO2)

XO = 3.3V (LDO3)

VDD = 3.3V (EXT. VIN1)

VDDO = 3.3V (EXT. VIN2)

XO = 3.3V (EXT. VIN3)

J500PWR
  • Pin 1 (VIN1): n/a
  • Pin 2 (VIN2): n/a
  • Pin 3 (VIN3): n/a
  • Pin 4 (VIN4): Connect to external 12V supply
  • Pin 5 (GND): Connect to supply ground
  • Pin 1 (VIN1): Connect to external 5V supply

  • Pin 2 (VIN2): n/a

  • Pin 3 (VIN3): n/a

  • Pin 4 (VIN4): n/a
  • Pin 5 (GND): Connect to supply ground
  • Pin 1 (VIN1): Connect to external 3.3V supply
  • Pin 2 (VIN2): Connect to external 3.3V supply
  • Pin 3 (VIN3): Connect to external 3.3V supply
  • Pin 4 (VIN4): n/a
  • Pin 5 (GND): Connect to supply ground
JP1VDD
  • Tie pins 1-2 (opposite to designator) to select 3.3V from DCDC to VDD Plane

  • Tie pins 3-4 (middle pins) to select 3.3V from LDO1 to VDD Plane

  • Tie pins 5-6 (adjacent to designator) to select external VIN1 to VDD Plane

JP2VDDO
  • Tie pins 1-2 (opposite to designator) to select 3.3V from DCDC to VDDO Plane
  • Tie pins 3-4 (middle pins) to select 3.3V from LDO2 to VDDO Plane

  • Tie pins 5-6 (adjacent to designator) to select external VIN2 to VDDO Plane

JP4XO
  • Tie pins 1-2 (opposite to designator) to select 3.3V from DCDC to XO supply
  • Tie pins 3-4 (middle pins) to select 3.3V from LDO3 to XO supply
  • Tie pins 5-6 (adjacent to designator) to select external VIN3 to XO supply