SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.9 SDI_OUT±, OUT0± and OUT1± Default Mode of Operation

By default, the OUT_CTRL pin (Pin 19) controls the OUT0±/SDI_OUT± and OUT1± mode behavior. To override this pin set the following register configuration.

Table 3-24 Override OUT_CTRL
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF0407//Select CDR Register Page
RAW

53

40

40

//Override OUT_CTRL pin. Output modes determined by register control.

When 0x53[6] is '1', 0x53[5:4] overwrites the selection from the OUT_CTRL pin.

Table 3-25 OUT_CTRL Settings
REG 0x53[5:4]

OUT0±, SDIOUT±

OUT1±
00

Cable EQ (CTLE, DFE) enabled and reclocker bypassed.

Cable EQ (CTLE, DFE) enabled and reclocker bypassed.

01Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabled

Full-Rate Recovered Clock if Data Rate ≤ 2.97Gbps. 297MHz Recovered Clock if Data Rate > 2.97Gbps

10Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabledRecovered Data, Cable EQ (CTLE, DFE) and reclocker enabled
11Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabledRecovered Data, Cable EQ (CTLE, DFE) and reclocker enabled

The following example can be used as a template to set the OUT0±/SDI_OUT± and OUT1± configuration:

Table 3-26 Override OUT_CTRL Settings
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF0407//Select CDR Register Page
RAW

53

40

40

//Override OUT_CTRL pin. Output modes determined by register control.
RAW

53

0030//L mode: Enable Bypass, Debug Only. OUT0, SDI_OUT, and OUT1: Equalized Data, Cable EQ (CTLE, DFE) enabled and reclocker bypassed
RAW

53

10

30

//R mode: Enable OUT0 and SDI_OUT: Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabled OUT1: Full-Rate Recovered Clock if Data Rate ≤ 2.97Gbps. 297MHz Recovered Clock if Data Rate > 2.97Gbps
RAW

53

20

30

//F mode: Enable Normal operation OUT0, SDI_OUT, and OUT1: Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabled
RAW

53

30

30

//H mode: Enable Normal operation OUT0, SDI_OUT, and OUT1: Recovered Data, Cable EQ (CTLE, DFE) and reclocker enabled