SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

CDR Loop Bandwidth Override

The LMH12x9 can be configured to a target CDR loop bandwidth through register control in the CDR page. To optimize jitter between the phase-locked loop (PLL) and voltage-controlled oscillator (VCO) the loop bandwidth can be adjusted over all data rates. TI recommends to leave the CDR loop bandwidth at default for the majority of cases.

Note:

An external 470nF loop filter capacitor is needed when LOOP_BW_SEL is R or L.

Table 3-13 Loop Bandwidth Table
DATA RATE (Gbps)LOOP_BW_SELEXTERNAL CAPACITOROVERRIDE & REG 0x23[6:7]TARGET CDR LOOP BW (0.2 UI SINUSOIDAL JITTER)

11.88

H

No

11

7MHz

F

No

01

7MHz

R

Yes

10

700kHz

L

Yes

00

350kHz

5.94

H

No

11

7MHz

F

No

01

7MHz

R

Yes

10

600kHz

L

Yes

00

300kHz

2.97

H

No

11

5MHz

F

No

01

5MHz

R

Yes

10

460kHz

L

Yes

00

230kHz

1.485

H

No

11

3MHz

F

No

01

3MHz

R

Yes

10

240kHz

L

Yes

00

120kHz

0.27

H

No

11

800kHz

F

No

01

800kHz

R

Yes

10

50kHz

L

Yes

00

30kHz

Table 3-14 Override the LOOP_BW_SEL pin
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF0407//Select CDR Register Page
RAW

24

80

80

//Override Loop_BW_SEL pin.

RAW2300C0//Set the Loop_BW_SEL in to L mode. Requires an external 470nF filter capacitor.

RAW

23

60

C0//Set the Loop_BW_SEL in to R mode. Requires an external 470nF filter capacitor.

RAW

23

80

C0

//Set the Loop_BW_SEL in to F mode

RAW

23

C0

C0

//Set the Loop_BW_SEL in to H mode