SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.12.1 Interrupt Outputs Programmed by Interrupt Registers

The following example enables all possible interrupts as outputs for the LOCK_N pin. The interrupts are treated as a logical OR function, so if at least one interrupt occurs, the LOCK_N pin asserts low.

Table 3-49 Interrupt Outputs Programmed by Interrupt Registers
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF3030//Interrupts are output on LOCK_N pin, determined by register settings
RAWFF0407//Select CDR Register Page
RAW

7F

4040//Enable interrupt if CDR lock is achieved
RAW

7F

2020//Enable interrupt if SDI_IN1± Signal Detect is asserted

RAW

7F

10

10

//Enable interrupt if SDI_IN± Signal Detect is asserted

RAW

7F

0808

//Enable interrupt when SDI-OUT+ detects a termination

RAW

7F

0404//Enable interrupt if CDR loses lock
RAW

7F

0202//Enable interrupt if there is loss of signal (LOS) on SDI_IN1±
RAW

7F

0101//Enable interrupt if there is loss of signal (LOS) on SDI_IN±
Note:

Interrupts are sticky bits. To clear the interrupt and thereby clear the LOCK_N pin, the user must read the corresponding bit in CDR Register Page Reg 0x7E. For example, if Reg 0x7F[6] = 1 to enable an interrupt for CDR lock, the interrupt remains asserted until Reg 0x7E[6] is read to clear the interrupt.

Table 3-50 Interrupt Outputs Programmed by Interrupt Registers
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF0407//Select CDR Register Page
RAR

7E

4040//Read interrupt if CDR lock is achieved
RAR

7E

2020//Read interrupt if SDI_IN1± Signal Detect is asserted

RAR

7E

10

10

//Read interrupt if SDI_IN1± Signal Detect is asserted

RAR

7E

0808//Read interrupt when SDI-OUT+ detects a termination

RAR

7E

0404//Read interrupt if CDR loses lock
RAR

7E

0202//Read interrupt if there is loss of signal (LOS) on SDI_IN1±
RAR

7E

0101//Read interrupt if there is loss of signal (LOS) on SDI_IN±