SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.1 Common Device Configuration

The LMH12x9 supports SMPTE applications up to 11.88Gbps (12G UHD-SDI). The choice of the input (SDI_IN± or SDI_IN1±, LMH1239 only), output controls, and reclocker enable are determined by the SDI_IN_SEL, SDI_OUT_ENA, OUT0_OUT1_SEL, and OUT_CTRL pins, respectively. A common configuration of the device is outlined in Table 3-2. If access to these pins is not available, the desired device configurations can still be accomplished by register override. Further details about specific configurations are provided in later sections of the programming guide.

Table 3-2 Select SDI_IN± or SDI_IN1± to OUT0± (Retimed Data) and OUT1± (Retimed Data)
COMMAND REGISTER VALUE MASK //COMMENTS

RAW

FF

05

07

//Enable EQ/Drivers Register Page

RAR

08

04

04

//Read back signal detect for SDI_IN±

RAR

08

01

01

//Read back signal detect for SDI_IN1±

RAW

FF

00

07

//Enable Share Register Page

RAW

FE

02

02

//Set IN_MUX_SEL pin override

RAW

FE

00

01

//Assuming signal is present on SDI_IN1±, select SDI_IN1±. To select SDI_IN±, write 0x01 to reg_FE[0]

RAW

FF

05

07

//Select EQ/Drivers Register Page

RAW

34

40

40

//Enable OUT0± Power Down Override

RAW

34

20

20

 //Disable OUT0± channels

RAW

34

00

20

//Enable OUT0± channels

RAW

36

40

40

//Enable OUT1± Power Down Override

RAW

36

20

20

 //Disable OUT1± channels

RAW

36

00

20

//Enable OUT1± channels