SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets

If a soft reset is performed by selecting the Reset Registers bit (regardless of the specific register page), users must re-initialize the LMH12x9 in order for the device to function properly. The LMH12x9 uses reserved SMBus accessible memory to control the internal state machine. At power up, this memory is automatically initialized; however, when resetting any register page, the state machine memory requires reinitialization.

Re-initialize the state machine by writing data 0x01 to register 0xE2 in the Share Register Page. Reinitialization of the state machine occurs in less than 100μs (maximum).

Reset and restore default register settings for the Share, the CDR, and the EQ/Drivers register pages:

Table 3-6 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
COMMANDREGISTERVALUEMASK//COMMENTS
RAWFF0007//Select Share Register Page
RAW044040//Reset Share Registers

RAW

FF

04

07

//Select CDR Register Page

RAW

00

04

04

//Reset CDR Registers

RAW

FF

05

07//Select EQ/Drivers Register Page

RAW

00

04

04

//Reset EQ/Drivers Registers

RAW

FF

00

07

//Select Share Register Page
RAWE20101//Reinitialize internal state machine register settings. Note: 0xE2[0] is not self-clearing. Any write of logic high triggers the initialization.
RARE21010//Poll and wait until 0xE2[4] is set to indicate internal state machine registers are initialized