SNAU305 User guide

SNAU305 February 2025 LMH1229 , LMH1239

4.3 EQ_Drivers Registers

Table 4-40 lists the memory-mapped registers for the EQ_Drivers registers. All register offset addresses not listed in Table 4-40 should be considered as reserved locations and the register contents should not be modified.

Table 4-40 EQ_DRIVERS Registers

Offset	Acronym	Register Name	Section
0h	General_Control	GEN_CTRL	Section 4.3.1
6h	Signal_Detect	SIG_DET1	Section 4.3.2
7h	Signal_Detect_2	SIG_DET2	Section 4.3.3
8h	Signal_Detect_3	SIG_DET3	Section 4.3.4
16h	CTLE_Index_Override	CTLE_OV	Section 4.3.5
30h	Mute_Reference_Threshold	MUTE_REF	Section 4.3.6
33h	OUT0_Controls	OUT0_CTRL	Section 4.3.7
34h	OUT0_Controls_2	OUT0_CTRL2	Section 4.3.8
35h	OUT1_Controls	OUT1_CTRL	Section 4.3.9
36h	OUT1_Controls_2	OUT1_CTRL2	Section 4.3.10
38h	SDI_OUT_Driver_Controls	SDI_OUTCTRL	Section 4.3.11
39h	Cable_Driver_VOD	CD_VOD	Section 4.3.12
3Ah	UHD_VOD_Adjustment	UHD_VOD	Section 4.3.13
3Bh	HD_VOD_Adjustment	HD_VOD	Section 4.3.14
3Ch	SD_VOD_Adjustment	SD_VOD	Section 4.3.15
3Fh	SDI_OUT_Pre-Emphasis	SDI_OUT_PE	Section 4.3.16
45h	DFE_Taps_1_Observation	DFE1	Section 4.3.17
47h	DFE_Taps_2_Observation	DFE2	Section 4.3.18
49h	DFE_Taps_3_Observation	DFE3	Section 4.3.19
7Eh	Coarse_Rate_Control	CRC	Section 4.3.20
9Ch	CTLE_Index	CTLE	Section 4.3.21
A8h	Cable_Fault_Detect	CFD	Section 4.3.22
ACh	Observation_Point_1	OBS1	Section 4.3.23
ADh	Observation_Point_2	OBS2	Section 4.3.24

Complex bit access types are encoded to fit into small table cells. Table 4-41 shows the codes that are used for access types in this section.

Table 4-41 EQ_Drivers Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

4.3.1 General_Control Register (Offset = 0h) [Reset = 08h]

General_Control is shown in Table 4-42.

Return to the Summary Table.

This register is for general control of the EQ/Drivers page.

Table 4-42 General_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	0h
4	RESERVED	R	0h
3	RESERVED	R	1h
2	register_reset	R/W1C	0h	Reset EQ/Drivers registers: 1'b0 = Normal operation 1'b1 = Reset EQ/Drivers registers
1	RESERVED	R	0h
0	RESERVED	R	0h

4.3.2 Signal_Detect Register (Offset = 6h) [Reset = 08h]

Signal_Detect is shown in Table 4-43.

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This register is for overriding the signal detect status on SDI_IN.

Table 4-43 Signal_Detect Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	0h
4	RESERVED	R	0h
3	dig_eq0_sd_ov	R/W	1h	Enable Override of Signal Detect on SDI_IN: 1'b0 = Normal operation 1'b1 = Override Signal Detect with value in bit 2 of this register
2	dig_eq0_sd	R/W	0h	Override Value for Signal Detect on SDI_IN: When bit 3 of this register is 1, this value is used in place of the Signal Detect. When bit 3 of this register is 0, this value is ignored.
1	RESERVED	R	0h
0	RESERVED	R	0h

4.3.3 Signal_Detect_2 Register (Offset = 7h) [Reset = 20h]

Signal_Detect_2 is shown in Table 4-44.

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This register is for overriding the signal detect status on SDI_IN1.

Table 4-44 Signal_Detect_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	1h
4	RESERVED	R	0h
3	dig_eq1_sd_ov	R/W	0h	Enable Override of Signal Detect on SDI_IN1: 1'b0 = Normal operation 1'b1 = Override Signal Detect with value in bit 2 of this register
2	dig_eq1_sd	R/W	0h	Override Value for Signal Detect on SDI_IN1: When bit 3 of this register is 1, this value is used in place of the Signal Detect. When bit 3 of this register is 0, this value is ignored.
1	RESERVED	R	0h
0	RESERVED	R	0h

4.3.4 Signal_Detect_3 Register (Offset = 8h) [Reset = 20h]

Signal_Detect_3 is shown in Table 4-45.

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This register is for viewing the signal detect status on SDI_IN and SDI_IN1.

Table 4-45 Signal_Detect_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	1h
4	RESERVED	R	0h
3	RESERVED	R	0h
2	eq0_sig_detect_filtered	R	0h	Signal detect status of SDI_IN: 1'b0 = No signal 1'b1 = Signal present
1	RESERVED	R	0h
0	eq1_sig_detect_filtered	R	0h	Signal detect status of SDI_IN1: 1'b0 = No signal 1'b1 = Signal present

4.3.5 CTLE_Index_Override Register (Offset = 16h) [Reset = 00h]

CTLE_Index_Override is shown in Table 4-46.

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This register is for overriding the CTLE index value.

Table 4-46 CTLE_Index_Override Register Field Descriptions

Bit	Field	Type	Reset	Description
7	eq_index_ov	R/W	0h	CTLE Adaptation Mode: 1'b0 = Fully Automatic 1'b1 = Manual control using bits[6:0]
6	eq_index_val_6	R/W	0h	Override EQ index value
5	eq_index_val_5	R/W	0h	See MSB
4	eq_index_val_4	R/W	0h	See MSB
3	eq_index_val_3	R/W	0h	See MSB
2	eq_index_val_2	R/W	0h	See MSB
1	eq_index_val_1	R/W	0h	See MSB
0	eq_index_val_0	R/W	0h	See MSB

4.3.6 Mute_Reference_Threshold Register (Offset = 30h) [Reset = 00h]

Mute_Reference_Threshold is shown in Table 4-47.

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This register is for setting the mute reference threshold. The mute reference threshold is defined as the threshold CTLE index + 2 for which OUT0/1 mute. The mute reference threshold is a binary value at 26mV per step.

Table 4-47 Mute_Reference_Threshold Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	reg_muteref_threshl_5	R/W	0h	Mute reference threshold value in decimal: 6'd0 = Mute when CTLE Index (eq boost) ≥ 2 6'd63 = Mute Reference threshold exceeds maximum CTLE, so the outputs never mute
4	reg_muteref_threshl_4	R/W	0h	See MSB
3	reg_muteref_threshl_3	R/W	0h	See MSB
2	reg_muteref_threshl_2	R/W	0h	See MSB
1	reg_muteref_threshl_1	R/W	0h	See MSB
0	reg_muteref_threshl_0	R/W	0h	See MSB

4.3.7 OUT0_Controls Register (Offset = 33h) [Reset = 3Fh]

OUT0_Controls is shown in Table 4-48.

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This register is for OUT0 control.

Table 4-48 OUT0_Controls Register Field Descriptions

Bit	Field	Type	Reset	Description
7	reg_tx0_mute_ov	R/W	0h	OUT0 Mute Override Control: 1'b0 = Disable OUT0 Mute Override Control 1'b1 = Enable OUT0 Mute Override Control by value in bit 6
6	reg_tx0_mute_val	R/W	0h	1'b0 = Normal Operation 1'b1 = Mute OUT0 if bit 7 is 1
5	RESERVED	R	1h
4	RESERVED	R	1h
3	reg_tx0_vod_ov	R/W	1h	OUT0 VOD override control: 1'b0 = VOD settings determined by VOD_DE pin 1'b1 = VOD settings controlled by bits [2:0]
2	reg_tx0_vod_2	R/W	1h	Override VOD settings: 3'b000 = 410mVpp 3'b010 = 560mVpp 3'b100 = 635mVpp 3'b110 = 810mVpp
1	reg_tx0_vod_1	R/W	1h	See MSB
0	reg_tx0_vod_0	R/W	1h	See MSB

4.3.8 OUT0_Controls_2 Register (Offset = 34h) [Reset = 12h]

OUT0_Controls_2 is shown in Table 4-49.

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This is the second register for OUT0 control.

Table 4-49 OUT0_Controls_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	reg_tx0_sel_inv	R/W	0h	Inverts driver polarity
6	reg_tx0_PD_ov	R/W	0h	Overrides for powering down the TX.
5	reg_tx0_PD	R/W	0h	1'b0 = Normal Operation 1'b1 = Power Down OUT0 if bit 6 is 1
4	reg_tx0_dem_ov	R/W	1h	If low, the DEM is taken from the VOD_DE pin. Otherwise, the DEM is taken from [3:0]
3	reg_tx0_dem_range	R/W	0h	Compresses DEM settings in [2:0] to <6dB when asserted
2	reg_tx0_dem_2	R/W	0h	De-emphasis settings: 3'b000 = 0.0dB 3'b010 = –1.0dB 3'b100 = –2.4dB 3'b110 = –6.1dB
1	reg_tx0_dem_1	R/W	1h	See MSB
0	reg_tx0_dem_0	R/W	0h	See MSB

4.3.9 OUT1_Controls Register (Offset = 35h) [Reset = 01h]

OUT1_Controls is shown in Table 4-50.

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This register is for OUT1 control.

Table 4-50 OUT1_Controls Register Field Descriptions

Bit	Field	Type	Reset	Description
7	reg_tx1_mute_ov	R/W	0h	OUT1 Mute Override Control: 1'b0 = Disable OUT1 Mute Override Control 1'b1 = Enable OUT1 Mute Override Control by value in bit 6
6	reg_tx1_mute_val	R/W	0h	1'b0 = Normal Operation 1'b1 = Mute OUT1 if bit 7 is 1
5	RESERVED	R	0h
4	RESERVED	R	0h
3	reg_tx1_vod_ov	R/W	0h	OUT1 VOD override control: 1'b0 = VOD settings determined by VOD_DE pin 1'b1 = VOD settings controlled by bits [2:0]
2	reg_tx1_vod_2	R/W	0h	Override VOD settings: 3'b000 = 410mVpp 3'b010 = 560mVpp 3'b100 = 635mVpp 3'b110 = 810mVpp
1	reg_tx1_vod_1	R/W	0h	See MSB
0	reg_tx1_vod_0	R/W	1h	See MSB

4.3.10 OUT1_Controls_2 Register (Offset = 36h) [Reset = 12h]

OUT1_Controls_2 is shown in Table 4-51.

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This is the second register for OUT1 control.

Table 4-51 OUT1_Controls_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	reg_tx1_sel_inv	R/W	0h	Inverts driver polarity
6	reg_tx1_PD_ov	R/W	0h	Overrides for powering-down the TX.
5	reg_tx1_PD	R/W	0h	1'b0 = Normal Operation 1'b1 = Power Down OUT1 if bit 6 is 1
4	reg_tx1_dem_ov	R/W	1h	If low, de-emphasis is taken from VOD_DE pin. Else, de-emphasis is taken from [3:0].
3	reg_tx1_dem_range	R/W	0h	Compresses DEM settings in [2:0] to <6dB when asserted.
2	reg_tx1_dem_2	R/W	0h	De-emphasis settings: 3'b000 = 0.0dB 3'b010 = –1.0dB 3'b100 = –2.4dB 3'b110 = –6.1dB
1	reg_tx1_dem_1	R/W	1h	See MSB
0	reg_tx1_dem_0	R/W	0h	See MSB

4.3.11 SDI_OUT_Driver_Controls Register (Offset = 38h) [Reset = 01h]

SDI_OUT_Driver_Controls is shown in Table 4-52.

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This register is for SDI_OUT driver control.

Table 4-52 SDI_OUT_Driver_Controls Register Field Descriptions

Bit	Field	Type	Reset	Description
7	sdi_out_PD_ov	R/W	0h	Override for SDI_OUT power-down control: 1'b0 = Use SDI_OUT_SEL pin to control SDI_OUT driver power-down 1'b1 = SDI_OUT power-down is controlled by bit 6
6	sdi_out_PD_val	R/W	0h	When bit 7 of this register is set: 1'b0 = SDI_OUT+/- enabled 1'b1 = SDI_OUT+/- disabled
5	RESERVED	R	0h
4	RESERVED	R	0h
3	RESERVED	R	0h
2	RESERVED	R	0h
1	RESERVED	R	0h
0	RESERVED	R	1h

4.3.12 Cable_Driver_VOD Register (Offset = 39h) [Reset = 68h]

Cable_Driver_VOD is shown in Table 4-53.

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This register is for overriding VOD from pin control and rate trim values with a baseline VOD value. See the SDI VOD Amplitude Control Logic block diagram in this document for more information on VOD control.

Table 4-53 Cable_Driver_VOD Register Field Descriptions

Bit	Field	Type	Reset	Description
7	sdi_out_vod_ov	R/W	0h	1'b0 = SDI_VOD pin control + data rate adjustment value (See the SDI VOD Amplitude Control Logic block diagram in this document for reference) 1'b1 = sdi_out_vod_val[6:0]
6	sdi_out_vod_val_6	R/W	1h	Default vod baseline for pin ctrl
5	sdi_out_vod_val_5	R/W	1h	See MSB
4	sdi_out_vod_val_4	R/W	0h	See MSB
3	sdi_out_vod_val_3	R/W	1h	See MSB
2	sdi_out_vod_val_2	R/W	0h	See MSB
1	sdi_out_vod_val_1	R/W	0h	See MSB
0	sdi_out_vod_val_0	R/W	0h	See MSB

4.3.13 UHD_VOD_Adjustment Register (Offset = 3Ah) [Reset = 0Ch]

UHD_VOD_Adjustment is shown in Table 4-54.

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This register is to apply adjustments to the output VOD on SDI_OUT for UHD.

Table 4-54 UHD_VOD_Adjustment Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	sdi_out_vod_os_uhd_sign	R/W	0h	SDI_OUT VOD control for UHD rates: 1'b0 = Positive 1'b1 = Negative
4	sdi_out_vod_os_uhd_4	R/W	0h	[4:0] = Magnitude in the range of 0mV to 194mV
3	sdi_out_vod_os_uhd_3	R/W	1h	See MSB
2	sdi_out_vod_os_uhd_2	R/W	1h	See MSB
1	sdi_out_vod_os_uhd_1	R/W	0h	See MSB
0	sdi_out_vod_os_uhd_0	R/W	0h	See MSB

4.3.14 HD_VOD_Adjustment Register (Offset = 3Bh) [Reset = 00h]

HD_VOD_Adjustment is shown in Table 4-55.

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This register is to apply adjustments to the output VOD on SDI_OUT for HD.

Table 4-55 HD_VOD_Adjustment Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	sdi_out_vod_os_hd_sign	R/W	0h	SDI_OUT VOD control for HD rates: 1'b0 = Positive 1'b1 = Negative
4	sdi_out_vod_os_hd_4	R/W	0h	[4:0] = Magnitude in the range of 0mV to 194mV
3	sdi_out_vod_os_hd_3	R/W	0h	See MSB
2	sdi_out_vod_os_hd_2	R/W	0h	See MSB
1	sdi_out_vod_os_hd_1	R/W	0h	See MSB
0	sdi_out_vod_os_hd_0	R/W	0h	See MSB

4.3.15 SD_VOD_Adjustment Register (Offset = 3Ch) [Reset = 00h]

SD_VOD_Adjustment is shown in Table 4-56.

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This register is to apply adjustments to the output VOD on SDI_OUT for SD.

Table 4-56 SD_VOD_Adjustment Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	sdi_out_vod_os_sd_sign	R/W	0h	SDI_OUT VOD control for SD rates: 1'b0 = Positive 1'b1 = Negative
4	sdi_out_vod_os_sd_4	R/W	0h	[4:0] = Magnitude in the range of 0mV to 194mV
3	sdi_out_vod_os_sd_3	R/W	0h	See MSB
2	sdi_out_vod_os_sd_2	R/W	0h	See MSB
1	sdi_out_vod_os_sd_1	R/W	0h	See MSB
0	sdi_out_vod_os_sd_0	R/W	0h	See MSB

4.3.16 SDI_OUT_Pre-Emphasis Register (Offset = 3Fh) [Reset = 30h]

SDI_OUT_Pre-Emphasis is shown in Table 4-57.

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This register is to apply changes to pre-emphasis on SDI_OUT.

Table 4-57 SDI_OUT_Pre-Emphasis Register Field Descriptions

Bit	Field	Type	Reset	Description
7	sdi_out_sel_pre_ov	R/W	0h	SDI_OUT pre-emphasis override control: 1'b0 = Normal operation 1'b1 = SDI_OUT pre-emphasis is controlled by bits [6:5]
6	sdi_out_sel_pre_val_1	R/W	0h	Pre-emphasis value: 2'b11 = 2.5dB
5	sdi_out_sel_pre_val_0	R/W	1h	See MSB
4	sdi_out_sel_pre_uhd	R/W	1h	1'b0 = Disable pre-emphasis at UHD data rates 1'b1 = Enable pre-emphasis value programmed in bits[6:5] at UHD data rates
3	sdi_out_sel_pre_hd	R/W	0h	1'b0 = Disable pre-emphasis at HD data rates 1'b1 = Enable pre-emphasis value programmed in bits[6 :5] at HD data rates
2	RESERVED	R	0h
1	RESERVED	R	0h
0	sdi_out_sel_inv	R/W	0h	1'b0 = Noninverting SDI_OUT output 1'b1 = Inverting SDI_OUT output

4.3.17 DFE_Taps_1_Observation Register (Offset = 45h) [Reset = 20h]

DFE_Taps_1_Observation is shown in Table 4-58.

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This register is the first observation point for DFE Taps.

Table 4-58 DFE_Taps_1_Observation Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	dfe_pol_1_obs	R	1h	DFE tap 1 polarity: 1'b0 = Positive 1'b1 = Negative
4	dfe_wt1_obs_4	R	0h	DFE tap 1 magnitude [4:0]
3	dfe_wt1_obs_3	R	0h	See MSB
2	dfe_wt1_obs_2	R	0h	See MSB
1	dfe_wt1_obs_1	R	0h	See MSB
0	dfe_wt1_obs_0	R	0h	See MSB

4.3.18 DFE_Taps_2_Observation Register (Offset = 47h) [Reset = 00h]

DFE_Taps_2_Observation is shown in Table 4-59.

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This register is the second observation point for DFE Taps.

Table 4-59 DFE_Taps_2_Observation Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	0h
4	dfe_pol_2_obs	R	0h	DFE tap 2 polarity: 1'b0 = Positive 1'b1 = Negative
3	dfe_wt2_obs_3	R	0h	DFE tap 2 magnitude [3:0]
2	dfe_wt2_obs_2	R	0h	See MSB
1	dfe_wt2_obs_1	R	0h	See MSB
0	dfe_wt2_obs_0	R	0h	See MSB

4.3.19 DFE_Taps_3_Observation Register (Offset = 49h) [Reset = 00h]

DFE_Taps_3_Observation is shown in Table 4-60.

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This register is the third observation point for DFE Taps.

Table 4-60 DFE_Taps_3_Observation Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	0h
4	dfe_pol_3_obs	R	0h	DFE tap 3 polarity: 1'b0 = Positive 1'b1 = Negative
3	dfe_wt3_obs_3	R	0h	DFE tap 3 magnitude [3:0]
2	dfe_wt3_obs_2	R	0h	See MSB
1	dfe_wt3_obs_1	R	0h	See MSB
0	dfe_wt3_obs_0	R	0h	See MSB

4.3.20 Coarse_Rate_Control Register (Offset = 7Eh) [Reset = 00h]

Coarse_Rate_Control is shown in Table 4-61.

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This register is to set the coarse EQ ending rate and the coarse EQ starting rate.

Table 4-61 Coarse_Rate_Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	ending_rate_det_register_reg_2	R/W	0h	Coarse EQ ending rate: 3'b000 = 12G 3'b001 = 6G 3'b010 = 3G 3'b011 = 1.5G 3'b100 = 270M (default) 3'b101, 3'b110, 3'b111 = Invalid
5	ending_rate_det_register_reg_1	R/W	0h	See MSB
4	ending_rate_det_register_reg_0	R/W	0h	See MSB
3	RESERVED	R	0h
2	starting_rate_det_register_reg_2	R/W	0h	Coarse EQ starting rate: 3'b000 = 12G (default) 3'b001 = 6G 3'b010 = 3G 3'b011 = 1.5G 3'b100 = 270M 3'b101, 3'b110, 3'b111 = Invalid
1	starting_rate_det_register_reg_1	R/W	0h	See MSB
0	starting_rate_det_register_reg_0	R/W	0h	See MSB

4.3.21 CTLE_Index Register (Offset = 9Ch) [Reset = 00h]

CTLE_Index is shown in Table 4-62.

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This register is to view the final CTLE index.

Table 4-62 CTLE_Index Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	ctle_index_5	R	0h	Adapted CTLE index from 0 to 55 in decimal notation
4	ctle_index_4	R	0h	See MSB
3	ctle_index_3	R	0h	See MSB
2	ctle_index_2	R	0h	See MSB
1	ctle_index_1	R	0h	See MSB
0	ctle_index_0	R	0h	See MSB

4.3.22 Cable_Fault_Detect Register (Offset = A8h) [Reset = 80h]

Cable_Fault_Detect is shown in Table 4-63.

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This register is used to enable the cable fault detector state machine.

Table 4-63 Cable_Fault_Detect Register Field Descriptions

Bit	Field	Type	Reset	Description
7	cfd_bypass	R/W	1h	Bypass the cable fault detector state machine
6	cfd_start	R/W1C	0h	Manual start cable fault detector state machine, self-cleared
5	cfd_disable	R/W	0h	Disable the cable fault detector state machine
4	RESERVED	R	0h
3	RESERVED	R	0h
2	RESERVED	R	0h
1	RESERVED	R	0h
0	RESERVED	R	0h

4.3.23 Observation_Point_1 Register (Offset = ACh) [Reset = 00h]

Observation_Point_1 is shown in Table 4-64.

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This register is the cable fault detection observation point.

Table 4-64 Observation_Point_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h
6	RESERVED	R	0h
5	RESERVED	R	0h
4	RESERVED	R	0h
3	sdi_out_term_status	R	0h	Cable fault detection status: 1'b0 = No termination detected on SDI_OUT 1'b1 = Termination detected on SDI_OUT
2	cfd_length_cnt_msb_2	R	0h	Cable length count MSB
1	cfd_length_cnt_msb_1	R	0h	MSB
0	cfd_length_cnt_msb_0	R	0h	MSB

4.3.24 Observation_Point_2 Register (Offset = ADh) [Reset = 00h]

Observation_Point_2 is shown in Table 4-65.

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This register is the second cable fault detect observation point.

Table 4-65 Observation_Point_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	cfd_length_cnt_lsb_7	R	0h	Cable length count LSB
6	cfd_length_cnt_lsb_6	R	0h	LSB
5	cfd_length_cnt_lsb_5	R	0h	LSB
4	cfd_length_cnt_lsb_4	R	0h	LSB
3	cfd_length_cnt_lsb_3	R	0h	LSB
2	cfd_length_cnt_lsb_2	R	0h	LSB
1	cfd_length_cnt_lsb_1	R	0h	LSB
0	cfd_length_cnt_lsb_0	R	0h	LSB