SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control

The LMH12x9 allows independent control of SDI_OUT±, OUT0± and OUT1±. The possible outputs are 10MHz clock for all three outputs, this requires an override in the share page to select 10MHz clock as an output, raw data, reclocked data, and mute. See the register writes below and the LMH1239EVM GUI for a simpler way of configuring the outputs.

To output a 10MHz clock, the LMH12x9 Signal Detect must detect an active signal at the selected input.

Table 3-27 SDI_OUT± 10MHz Clock
COMMAND REGISTER VALUE MASK //COMMENTS

RAW

FF

00

07

 //Select Share Register Page

RAW

0C

80

80

//Selects 10MHz clock on outputs as opposed to VCO/40 rate clock
RAW FF 04 07 //Select CDR Register Page
RAW

53

62

72

 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally
RAW

54

 02 03 //Enable 10MHz clock output on SDI_OUT±
Table 3-28 SDI_OUT± Raw Data
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 04 07 //Select CDR Register Page
RAW

53

 62 72 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally
RAW 54 00 03 //Output Raw data (EQ only) on SDI_OUT±
Table 3-29 SDI_OUT± Reclocked Data
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 04 07 //Select CDR Register Page
RAW 53

62

 72 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally
RAW 54 01 03 //Output reclocked data on SDI_OUT± (valid only in locked condition)
Table 3-30 OUT0± Raw Data
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 04 07 //Select CDR Register Page
RAW 53 62 72 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally
RAW

54

 00

E0

 //Output raw data (EQ only) on OUT0±
Table 3-31 OUT0± Mute
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 04 07 //Select CDR Register Page
RAW

53

62

72

 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally
RAW

54

E0

E0

 //Mute OUT0±
Table 3-32 OUT0± Reclocked Data
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 04 07 //Select CDR Register Page
RAW

53

02

02

 //Enable Independent Output Control Override
RAW

54

20

E0

 //Output reclocked data on OUT0± (valid only in locked condition)

To output a 10MHz clock, the LMH12x9 Signal Detect must detect an active signal at the selected input. However, the LMH12x9 does not need to be locked. SDI_OUT± does not need to output a 10MHz clock for OUT0± to output a 10MHz clock. To set the independent output control settings for OUT1±, see the register map and EVM GUI.

Table 3-33 OUT0± 10MHz Clock
COMMAND REGISTER VALUE MASK //COMMENTS
RAW FF 00 07 //Select Share Register Page
RAW 0C 80 80 //Selects 10MHz clock on outputs as opposed to VCO/40 rate clock
RAW FF 04 07 //Select CDR Register Page
RAW 53 62 72 //Enable Independent Output Control Override and ensure that CDR and EQ blocks operate normally

RAW

54

A0

E0

 //Output 10MHz on OUT0±