SNAU305 February   2025 LMH1229 , LMH1239

 

  1.   1
  2.   LMH1229 and LMH1239 Programming Guide
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Register Programming Through SPI
    3. 1.3 Register Pages
  5. 2Register Command Syntax
  6. 3Device Configurations
    1. 3.1  Common Device Configuration
    2. 3.2  Common Register Commands
      1. 3.2.1 Channel Control
      2. 3.2.2 LMH12x9 Resets
        1. 3.2.2.1 LMH12x9 ENABLE Pin Override
        2. 3.2.2.2 LMH12x9 Share, CDR, and EQ/Drivers Page Resets
    3. 3.3  IN_MUX_SEL Override
    4. 3.4  Signal Detect Status for SDI_IN± and SDI_IN1±
      1. 3.4.1 Force Signal Detect Power Down
    5. 3.5  Lock Data Rate Indication
    6. 3.6  CDR Loop Bandwidth Override
    7. 3.7  Selective SMPTE Data Rate Lock
      1. 3.7.1 Digital Mute Reference Threshold
      2. 3.7.2 CTLE Index Check and Manual CTLE Override
    8. 3.8  Eye Opening Monitoring Operation
      1. 3.8.1 Fast EOM
        1. 3.8.1.1 Fast EOM Operation
      2. 3.8.2 Read Horizontal and Vertical Eye Opening
    9. 3.9  SDI_OUT±, OUT0± and OUT1± Default Mode of Operation
      1. 3.9.1 SDI_OUT±, OUT0± and OUT1± Independent Control
    10. 3.10 Invert OUT0±, OUT1±, and SDI_OUT± Data Polarity
    11. 3.11 OUT0±, OUT1±, and SDI_OUT± Driver Settings
      1. 3.11.1 OUT0± and OUT1± VOD Settings
      2. 3.11.2 OUT0± and OUT1± De-Emphasis Settings
      3. 3.11.3 SDI_OUT± VOD Settings
      4. 3.11.4 SDI_OUT± Pre-Emphasis
      5. 3.11.5 Output Driver Power Down
      6. 3.11.6 Cable Fault Detection (CFD)
    12. 3.12 LOCK_N Pin Output Settings
      1. 3.12.1 Interrupt Outputs Programmed by Interrupt Registers
    13. 3.13 PRBS Generator and Checker
    14. 3.14 CDR Lock Timing Control
      1. 3.14.1 Watchdog Timer
  7. 4Register Maps
    1. 4.1 Share Registers
    2. 4.2 CDR Registers
    3. 4.3 EQ_Drivers Registers

3.13 PRBS Generator and Checker

The LMH12x9 can be configured to output PRBS-7, PRBS-9, PRBS-23 and PRBS-31. Based on the PRBS polynomial and polarity selected, data is generated after loading the initial seed. The 32-bit data generated is read by the serializer clock. The pattern can be output to SDI_OUT±, OUT0± and/or OUT1±.

Table 3-51 PRBS Generator
COMMANDREGISTERVALUEMASK//COMMENTS

RAW

FF

04

07

//Select CDR Register Page

RAW

2C

80

C0

//Enable the VCO by enabling the VCO_PD override and writing 0 to VCO_PD

RAW

45

88

CE

//Enable PFD

RAW

41

80

C0

//Enable Deserializer

RAW

3F

00

20

//Enable PDIQ

RAW

3F

00

07

//Select VCO Scalar Divider

//Reg0x3F[2:0] = 3'b000 Full-Rate

//Reg0x3F[2:0] = 3'b001 Divide-by-2

//Reg0x3F[2:0] = 3'b010 Divide-by-4

//Reg0x3F[2:0] = 3'b011 Divide-by-8

//Reg0x3F[2:0] = 3'b100 Divide-by-40

RAW

3F

08

08

//Enable PDIQ Override

RAW

3F

48

48

//Enable PDIQ PD Override

RAW

54

80

E0

//Reg0x54[7:5] = 3'b100 PRBS data on OUT0

10

1C

//Reg0x54[4:2] = 3'b100 PRBS data on OUT1

03

03

//Reg0x54[1:0] = 2'b11 PRBS data on SDI_OUT

RAW

53

02

02

//Override the independent output control

RAW

40

20

20

//Enable Serializer

RAW

82

40

40

//Allow serializer clock to drive PRBS-core

RAW

FF

05

07

//Select EQ/Drivers Register Page

RAW

34

40

40

//Disable ability to power down TX0

RAW

36

40

40

//Disable ability to power down TX1

RAW

38

80

80

//Disable ability to power down SDI_OUT±

RAW

FF

00

07

//Select SHARE Register Page

RAW

0C

04

04

//Hold serializer clock in reset state

RAW

0B

04

04

//Enable Serializer Clock

RAW

0C

00

04

//Bring serializer clock out of reset state

RAW

FF

04

07

//Select CDR Register Page

RAW

79

00

30

//Reg0x79[5:4] = 2'b00 PRBS7

10

30

//Reg0x79[5:4] = 2'b01 PRBS9

20

30

//Reg0x79[5:4] = 2'b10 PRBS23

30

30

//Reg0x79[5:4] = 2'b11 PRBS31

RAW

7A

00

01

//Force no polarity inversion on gen data

RAW

79

02

02

//Make the logic as PRBS generator

RAW

79

01

01

//Enable PRBS functionality

RAW

FF

00

07

//Select SHARE Register Page

RAW

FE

08

0C

//Overrides for OUT0±

When the LMH12x9 is programmed in generator mode the device can generate error-free PRBS. It is possible to inject one bit of error to the generated data by flipping one of the bits in the generated data. The user can assign the error to one of the 32 bits by setting the self clearing inject-bit. After this action, the output data carries one bit error.

Table 3-52 Bit Error Injection
COMMANDREGISTERVALUEMASK//COMMENTS

RAW

FF

04

07

//Select CDR Register Page

RAW

82

xx

1F

//0x82[4:0] = 5'bxxxxx Select 32-bit address for single-bit error injection

RAW

82

20

20

//Trigger the PRBS generator to inject just one bit of error in the generated data stream. Self-clearing.

If the module is set to check PRBS, the incoming deserializer data is first loaded to the device as a seed. Based on the PRBS polynomial and polarity selected by the state machine, the device generates a new value, and this value is compared against the deserializer data in the next data clock cycle. This process repeats for 64 clock cycles and if the data from device matches the deserializer data in all 64 clock cycles, the state machine (SM) declares a PRBS-lock, which means the SM finds a matching PRBS polynomial in the incoming data. Otherwise, the SM switch to test the opposite polarity, and then another polynomial. This process repeats until the SM finds a PRBS lock. However, if the incoming signal does not match any of the supported PRBS polynomial, this process goes on forever.

Table 3-53 PRBS Checker
COMMANDREGISTERVALUEMASK//COMMENTS

RAW

FF

04

07

//Select CDR Register Page

RAW

40

20

20

//Initialize clock signals for PRBS checking

RAW

82

40

40

//Initialize clock signals for PRBS checking

RAW

82

00

40

//Initialize clock signals for PRBS checking

RAW

40

00

20

//Initialize clock signals for PRBS checking

RAW

8B

00

80

///Turn off power cycling

RAW

82

80

80

//Allow deserializer clock to drive PRBS-core

RAW

79

04

04

//Make the logic as PRBS Checker

RAW

79

10

10

//Enable PRBS functionality

RAR

73

0F

//Read PRBS_PATT_DET to detect which PRBS is being provided

//Reg 0x73[3:0] = 4'b1000 PRBS-31 Detected

//Reg 0x73[3:0] = 4'b0100 PRBS-23 Detected

//Reg 0x73[3:0] = 4'b0010 PRBS-9 Detected

//Reg 0x73[3:0] = 4'b0001 PRBS-7 Detected

RAR

74

07

//Read upper three bits of eleven-bit wide error sum. Maximum 2047 total errors.

//Reg0x74[2:0] = 3'bxxx

RAR

75

FF

//Read lower eight bits of eleven-bit wide error sum

//Reg0x75[7:0] = 8'bxxxxxxxx