SPRACW5A April   2021  – December 2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2ACI Motor Control Benchmark Application
    1. 2.1 Source Code
    2. 2.2 CCS Project for TMS320F28004x
    3. 2.3 CCS Project for TMS320F2837x
    4. 2.4 Validate Application Behavior
    5. 2.5 Benchmarking Methodology
      1. 2.5.1 Details of Benchmarking With Counters
    6. 2.6 ERAD Module for Profiling Application
  4. 3Real-time Benchmark Data Analysis
    1. 3.1 ADC Interrupt Response Latency
    2. 3.2 Peripheral Access
    3. 3.3 TMU (math enhancement) Impact
    4. 3.4 Flash Performance
    5. 3.5 Control Law Accelerator (CLA)
      1. 3.5.1 Full Signal Chain Execution on CLA
        1. 3.5.1.1 CLA ADC Interrupt Response Latency
        2. 3.5.1.2 CLA Peripheral Access
        3. 3.5.1.3 CLA Trigonometric Math Compute
      2. 3.5.2 Offloading Compute to CLA
  5. 4C2000 Value Proposition
    1. 4.1 Efficient Signal Chain Execution With Better Real-Time Response Than Higher Computational MIPS Devices
    2. 4.2 Excellent Real-Time Interrupt Response With Low Latency
    3. 4.3 Tight Peripheral Integration That Scales Applications With Large Number of Peripheral Accesses
    4. 4.4 Best in Class Trigonometric Math Engine
    5. 4.5 Versatile Performance Boosting Compute Engine (CLA)
    6. 4.6 Deterministic Execution due to Low Execution Variance
  6. 5Summary
  7. 6References
  8. 7Revision History

2.2 CCS Project for TMS320F28004x

The project can be imported in CCS using "Import Project" option and selecting the project located at 'f28004x\ccs'. The project comes with several pre-defined build configurations. Once the project is imported, the project can be built for these different build configurations that are described below:

  • SignalChain_RAM_TMU: The application compiles for the full signal chain executing out of RAM using the TMU instructions for control algorithms like Park and Inverse Park that use trigonometric math. The build setting is controlled by the defines SIGNAL_CHAIN=1 and USE_FAST_TRIG_LIB=0.
  • SignalChain_FLASH_TMU: The application compiles for the full signal chain similar to the SignalChain_RAM_TMU except that it executes out of FLASH. The build setting is controlled by the defines SIGNAL_CHAIN=1, USE_FAST_TRIG_LIB=0 and _FLASH.
  • SignalChain_RAM_FastRTS: The application compiles for the full signal chain executing out of RAM using the FastRTS library instead of TMU for control algorithms like Park, Inverse Park that use trigonometric math. The build setting is controlled by the defines SIGNAL_CHAIN=1 and USE_FAST_TRIG_LIB=1.
  • SignalChain_FLASH_FastRTS: The application compiles for the full signal chain similar to the SignalChain_RAM_FastRTS except that it executes out of Flash. The build setting is controlled by the defines SIGNAL_CHAIN=1, USE_FAST_TRIG_LIB=1 and _FLASH.
  • ControlAlgo_RAM_TMU: The application compiles for just the control algorithm and not the full signal chain, that is, peripherals are not configured and interrupts are not generated in this build configuration. This can be used as a starting point for porting this application to other devices. The build setting is controlled by the defines SIGNAL_CHAIN=0 and USE_FAST_TRIG_LIB=0.
  • SignalChain_RAM_TMU_CLA_OFFLOAD: The application compiles for the full signal chain executing out of RAM using the TMU instructions for control algorithms like Park and Inverse Park that use trigonometric math on the C28x CPU side. The C28x CPU offloads some of the control code compute to CLA resulting in parallelized execution. The build setting is controlled by the defines SIGNAL_CHAIN=1, USE_FAST_TRIG_LIB=0 and CLA_OFFLOAD.
  • SignalChain_FLASH_TMU_CLA_OFFLOAD: The application compiles for the full signal chain similar to the SignalChain_RAM_TMU except that the C28x CPU code executes out of FLASH. The build setting is controlled by the defines SIGNAL_CHAIN=1, USE_FAST_TRIG_LIB=0, CLA_OFFLOAD and _FLASH.
  • SignalChain_RAM_CLAmath_CLA: The application compiles for the full signal chain executing out of RAM from CLA using the CLAmath library for control algorithms like Park and Inverse Park that use trigonometric math as unlike C28x CPU, the CLA accelerator does not have a TMU. The build setting is controlled by the defines SIGNAL_CHAIN=1, USE_FAST_TRIG_LIB=0 and CLA_CPU.

Once the application is built, load the application to the target and select the run option in CCS to execute the application.

The data from the seven SignalChain build configurations are used in this application report to compare TMU vs FastRTS execution, RAM vs Flash execution and CLA execution.