SPRT759B October   2023  – June 2026 F28377D-SEP , F29H850DM , F29H850TU , F29H859TU-Q1 , F29P329SM-Q1 , F29P589DM-Q1 , F29P589DU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Overview of IEC 60730 and UL 1998 Classifications
    1.     C2000 Capability by Device Family
  6. 3C2000 Safety Collateral
    1.     Getting Started
    2.     Functional Safety Manuals
    3.     Software Collateral
  7. 4Implementing Acceptable Measures on C2000 Real-Time MCUs
    1.     Implementation Steps
    2.     Example Mapping
    3.     Additional Best Practices
  8. 5Mapping Acceptable Control Measures to C2000 Unique Identifiers
    1.     Unique Identifier Reference
    2. 5.1 F28002x, F280013x, F280015x, F28E12x Mapping
      1. 5.1.1 CPU Related Faults
      2. 5.1.2 Interrupt Related Faults
      3. 5.1.3 Clock Related Faults
      4. 5.1.4 Memory Related Faults
      5. 5.1.5 Internal Data Path Faults
      6. 5.1.6 Input/Output Related Faults
    3. 5.2 F28004x, F28003x, F28P55x Mapping
      1. 5.2.1 CPU Related Faults
      2. 5.2.2 Interrupt Related Faults
      3. 5.2.3 Clock Related Faults
      4. 5.2.4 Memory Related Faults
      5. 5.2.5 Internal Data Path Faults
      6. 5.2.6 Input/Output Related Faults
    4. 5.3 F2837x, F2838x, F28P65x Mapping
      1. 5.3.1 CPU Related Faults
      2. 5.3.2 Interrupt Related Faults
      3. 5.3.3 Clock Related Faults
      4. 5.3.4 Memory Related Faults
      5. 5.3.5 Internal Data Path Faults
      6. 5.3.6 Input/Output Related Faults
    5. 5.4 F29H85x, F29P85x, F29P32x Mapping
      1. 5.4.1 CPU Related Faults
      2. 5.4.2 Interrupt Related Faults
      3. 5.4.3 Clock Related Faults
      4. 5.4.4 Memory Related Faults
      5. 5.4.5 Internal Data Path Faults
      6. 5.4.6 Input/Output Related Faults
    6.     Communication, Monitoring Devices, and Custom Chip Faults
  9. 6Glossary
  10. 7References
  11. 8Revision History

5.3.4 Memory Related Faults

Table 5-17 Memory Faults to Unique ID Mapping
ComponentClass B/1 (1)Class C/2 (1)Acceptable Measure (2)C2000 Unique IDs (3)
DefinitionDescriptionF2837x
F2807x

F2838x

F28P65x

4.1 Non-volatilerqH.2.19.3.2
A7.2.5		Multiple checksum--ROM10
H2.19.8.2
A7.3.2		Word protection, single-bit parity--ROM15
rqH.2.18.15
A7.1.19		Reciprocal comparisonCPU1CPU1CPU1
CLA1CLA1CLA1
H.2.18.3
A7.1.6		Independent hardware comparator--CPU21
H.2.19.5
A7.2.8		Redundant memory with comparisonDCSM2DCSM2DCSM2
H.2.19.4.2
A7.2.7		Periodic CRC, double wordFLASH2FLASH2NWFLASH5
ROM1ROM1ROM1
--

-

--ROM13
H2.19.8.1
A7.3.1		Word protection with multi-bit redundancyFLASH1FLASH1NWFLASH1
EFUSE2EFUSE2

-

4.2 VolatilerqH.2.19.6
A7.2.9		Periodic static memory testSRAM3SRAM3SRAM3
H2.19.8.2
A7.3.2		Word protection, single-bit paritySRAM2SRAM2SRAM2
CAN3CAN3CAN3
-ECAT6ECAT6
--

-

rqH2.19.5
A7.2.8		Redundant memory with comparisonPIE1PIE1PIE1
H.2.19.8.1
A7.3.1		Word protection, multi-bit redundancySRAM1SRAM1SRAM1
-MCAN8MCAN8
4.3 Addressing (volatile and non-volatile memory)rqH2.19.8.2
A7.2.9		Word protection, single-bit paritySRAM2SRAM2SRAM2
--ROM15
CAN3CAN3CAN3
-ECAT6ECAT6
--

-

rqH.2.19.4.2
A7.2.7		Periodic CRC - double wordSRAM8 (4)SRAM8SRAM8
-SRAM24SRAM24
FLASH2FLASH2NWFLASH2
ROM1ROM1ROM1
--

-

--ROM13
H.2.19.8.1
A7.3.1		Word protection, multi-bit redundancy including addressFLASH1FLASH1

NWFLASH1

SRAM1SRAM1SRAM1

-

MCAN8MCAN8
(1) rq: coverage of the failure mode (refer to Table 2-2) is required by the standards for the indicated class. More than one acceptable measure may be available to choose from.
(2) For a complete list of acceptable measures and their definitions, see the IEC / UL specifications.
(3) For a description and implementation suggestions for each ID, see the device-specific Functional Safety Manual.
(4) The F2807x, F280013x, and F28E12x devices do not have a VCRC module. The CRC is performed by the CPU. For more information, see the device-specific software diagnostic library.