SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 8-43 lists the memory-mapped registers for the VIMS registers. All register offset addresses not listed in Table 8-43 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | STAT | Status | Section 8.6.2.1 |
4h | CTL | Control | Section 8.6.2.2 |
Complex bit access types are encoded to fit into small table cells. Table 8-44 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
STAT is shown in Table 8-45.
Return to the Summary Table.
Status
Displays current VIMS mode and line buffer status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | IDCODE_LB_DIS | R | 0h | Icode/Dcode flash line buffer status 0: Enabled or in transition to disabled 1: Disabled and flushed |
4 | SYSBUS_LB_DIS | R | 0h | Sysbus flash line buffer control 0: Enabled or in transition to disabled 1: Disabled and flushed |
3 | MODE_CHANGING | R | 0h | VIMS mode change status 0: VIMS is in the mode defined by MODE 1: VIMS is in the process of changing to the mode given in CTL.MODE |
2 | INV | R | 0h | This bit is set when invalidation of the cache memory is active / ongoing |
1-0 | MODE | R | 0h | Current VIMS mode
0h = GPRAM : VIMS GPRAM mode 1h = CACHE : VIMS Cache mode 3h = VIMS Off mode |
CTL is shown in Table 8-46.
Return to the Summary Table.
Control
Configure VIMS mode and line buffer settings
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | STATS_CLR | R/W | 0h | Set this bit to clear statistic counters. |
30 | STATS_EN | R/W | 0h | Set this bit to enable statistic counters. |
29 | DYN_CG_EN | R/W | 0h | 0: The in-built clock gate functionality is bypassed. 1: The in-built clock gate functionality is enabled, automatically gating the clock when not needed. |
28-6 | RESERVED | R | 0h | Reserved |
5 | IDCODE_LB_DIS | R/W | 0h | Icode/Dcode flash line buffer control 0: Enable 1: Disable |
4 | SYSBUS_LB_DIS | R/W | 0h | Sysbus flash line buffer control 0: Enable 1: Disable |
3 | ARB_CFG | R/W | 0h | Icode/Dcode and sysbus arbitation scheme 0: Static arbitration (icode/docde > sysbus) 1: Round-robin arbitration |
2 | PREF_EN | R/W | 0h | Tag prefetch control 0: Disabled 1: Enabled |
1-0 | MODE | R/W | 0h | VIMS mode request. Write accesses to this field will be blocked while STAT.MODE_CHANGING is set to 1. 0h = GPRAM : VIMS GPRAM mode 1h = CACHE : VIMS Cache mode 3h = VIMS Off mode |