TIDUF75 April   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 System Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1  Determining the Number of eFuse Devices to use in Parallel
      2. 2.2.2  Setting up the Primary and Secondary Devices in a Parallel Configuration
      3. 2.2.3  Selecting the CDVDT Capacitor to Control the Output Slew Rate and Start-Up Time
      4. 2.2.4  Selecting the RIREF Resistor to set the Reference Voltage for Overcurrent Protection and Active Current Sharing
      5. 2.2.5  Selecting the RIMON Resistor to set the Overcurrent (Circuit Breaker) and Fast-Trip Thresholds During Steady-State
      6. 2.2.6  Selecting the RILIM Resistor to set the Current Limit and Fast-Trip Thresholds During Start-Up and the Active Sharing Threshold During Steady-State
      7. 2.2.7  Selecting the CITIMER Capacitor to Set the Overcurrent Blanking Timer
      8. 2.2.8  Selecting the Resistors to set the Under-voltage Lockout Threshold
      9. 2.2.9  Selecting the R-C Filter Between VIN and VDD
      10. 2.2.10 Selecting the Pullup Resistors and Power Supplies for SWEN, PG, FLT, and CMPOUT Pins
      11. 2.2.11 TVS Diode Selection at Input and Schottky Diode Selection at Output
      12. 2.2.12 Selecting CIN and COUT
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS25985
      2. 2.3.2 LM94022 and LM94022-Q1
      3. 2.3.3 INA241x
      4. 2.3.4 TLV760
      5. 2.3.5 SN74LVC1G123
      6. 2.3.6 UCC27511A
      7. 2.3.7 CSD18510Q5B
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1.      36
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 Bill of Materials
      3. 4.1.3 Altium Project
      4. 4.1.4 Gerber Files
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.3 Selecting the CDVDT Capacitor to Control the Output Slew Rate and Start-Up Time

For a robust design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of magnitude greater than static stresses. Therefore, establishing the right start-up time and inrush current limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up is crucial.

Table 2-1 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence of different loads during start-up if the power-good (PG) signal is not used to turn on all the downstream loads.

Table 2-1 Calculation of Average Power Loss During Inrush
Type of Loads During Start-Up Expressions to Calculate the Average Inrush Power Loss
Only output capacitor of CLOAD (µF)
Equation 2. V I N 2 C L O A D 2 T s s
Output capacitor of CLOAD (µF) and constant resistance of RLOAD(Startup) (Ω) with turn-on threshold of VRTH (V)
Equation 3. V I N 2 C L O A D 2 T s s + V I N 2 R L O A D ( S t a r t u p ) 1 6 - 1 2 V R T H V I N 2 + 1 3 V R T H V I N 3
Output capacitor of CLOAD (µF) and constant current of ILOAD(Startup) (A) with turn-on threshold of VCTH (V)
Equation 4. V I N 2 C L O A D 2 T s s + V I N I L O A D ( S t a r t u p ) 1 2 - V C T H V I N + 1 2 V C T H V I N 2
Output capacitor of CLOAD (µF) and constant power of PLOAD(Startup) (W) with turn-ON threshold of VPTH (V)
Equation 5. V I N 2 C L O A D 2 T s s + P L O A D ( S t a r t u p ) ln ⁡ V P T H V I N + V P T H V I N - 1

where

  • VIN is the input voltage
  • Tss is the start-up time

With the different combinations of loads during start-up, the total average inrush power loss (PINRUSH) can be calculated using the formulas described in Table 2-1. For a successful start-up, the system must satisfy the condition stated in Equation 6.

Equation 6. P I N R U S H W T s s s < 12 × N

where

  • N denotes the number of eFuses in parallel
  • 12 W√s is the SOA limit of a single TPS25985x eFuse

Use Equation 7 to obtain the maximum allowed Tss.

Note: TI recommends using a Tss in the range of 5ms to 120ms to prevent start-up issues.

A capacitor (CDVDT) must be added at the DVDT pin to GND to set the required value of Tss as previously calculated. Equation 7 is used to compute the value of CDVDT. The DVDT pins of all the eFuses in a parallel chain must be connected together.

Equation 7. C D V D T p F = 42000 V I N V / T s s m s

Using VIN = 12V, Tss = 10ms, and Equation 7, the required CDVDT value can be calculated to be 35nF. The closest standard value of CDVDT is 33nF with 10% tolerance and a DC voltage rating of 25V.

Note: In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-on threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action makes sure that the load is turned on only when the eFuse has completed start-up and is ready to deliver full power without the risk of hitting thermal shutdown.