TIDUFF8 September 2025
Figure 3-3 shows the schematic of the inductive AFE for the outer sense coil. The comments apply to the schematic for the inner sense coil too.
Three decoupling capacitors (C10, C42, and C44) are added close to LDC5072 VCC and the GND pin. C43 and C45 are decoupling capacitors placed close to VREG and the GND pin.
The LDC5072 device supports both 3.3V and 5V supply voltage at VCC. If 3.3V is supplied, both VCC and VREG are supplied from an external 3.3V power supply and R65 needs to be populated. If 5V is supplied, the LDC5072 uses an internal LDO to generate 3.3V for VREG and R65 needs to be removed.
The LDC5072 device supports both fixed-gain mode and automatic gain control (AGC) mode. R63 and R64 are resistor divider which control the gain setting. This reference design does not populate R64, making the LDC5072 device run in AGC mode.
C60, C61 (470pF), and the excitation coil on the sense coil PCB form the LC circuit. The outer excitation inductance (L) of the coil is design as 5μH, so the resonant frequency of the LC circuit is 4.6MHz and can be calculated in formula:
R51, C55, R54, C56, R56, C57 and R59, and C58 implement the low-pass filter for the sensor coil sine and cosine output.
C47, C48, C49, and C50 are 10nF and form a low-pass filter with the LDC5072 output impedance. For higher speeds, reduce the capacitors and see the data sheet for selection of the capacitor.