TIDUFF8 September   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LDC5072-Q1
      2. 2.3.2 MSPM0G3507
      3. 2.3.3 TPSM365R3
      4. 2.3.4 TLV9062
  9. 3System Design Theory
    1. 3.1 Hardware Design
      1. 3.1.1 Target PCB
      2. 3.1.2 Coil PCB
      3. 3.1.3 Signal Chain PCB
        1. 3.1.3.1 Inductive Angle Position Sensor Front-End Schematic
        2. 3.1.3.2 Differential to Single-Ended Signal Conversion
      4. 3.1.4 MSPM0G3507 Schematic Design
      5. 3.1.5 Power Supply Design
    2. 3.2 Absolute Position Calculation
    3. 3.3 Software Design
      1. 3.3.1 Angle Calculation Timing
      2. 3.3.2 Rotary Angle Error Sources and Compensation
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 PCB Overview
      2. 4.1.2 Encoder Interface
    2. 4.2 Software
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Inductive Sensor Sine and Cosine Noise Measurement
      2. 4.4.2 Absolute Angle Noise Measurement
      3. 4.4.3 Rotary Angle Accuracy Measurement
      4. 4.4.4 Impact of Air Gap on Noise, 4th Electrical Harmonics and Total Angle Accuracy
      5. 4.4.5 Power Consumption Measurement
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout
      4. 5.1.4 Altium Project Files
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5.     Trademarks
  12. 6About the Author

3.1.4 MSPM0G3507 Schematic Design

The ceramic decoupling capacitors C3(10µF) and C4(1µF) are placed across the VDD and VSS pins, and C1(100nF), C2(0.47µF) are placed across the VCORE and VSS pins. A ferrite bead FB1 is added between VDD and the 3.3V power rail to avoid the high-frequency digital current populating the analog signal.

The NRST reset pin is pulled up to VDD with a 47kΩ resistor (R2) and 10nF pulldown capacitor (C7). The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100kΩ with 0.1% tolerance resistor R5 populated between the ROSC pin and VSS.

MSPM0 accepts external ADC reference to improve ADC ENOB. In TIDA-010961, REF3533 is used as external reference and whose outputs are connected to the VREF+ and VREF– pins of M0. The C10(100nF) decoupling capacitor is placed across VREF+ and VREF–.

TIDA-010961 MSPM0G3507 Schematic Figure 3-5 MSPM0G3507 Schematic