TIDUFG2 December   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Sensor Selection
    3. 2.3 Highlighted Products
      1. 2.3.1 TLV387
      2. 2.3.2 TLV9054
      3. 2.3.3 MSPM0G5187-LP
      4. 2.3.4 LOG300
      5. 2.3.5 UCC28881
      6. 2.3.6 TPS709
  9. 3System Design Theory
    1. 3.1 Current Sensor
    2. 3.2 Hybrid Integrator
    3. 3.3 Band-Pass Filter
      1. 3.3.1 Log Amplifier
      2. 3.3.2 Current Low-Pass Filter
      3. 3.3.3 Non-isolated Voltage Sensing
      4. 3.3.4 Auto Labeling Circuit
        1. 3.3.4.1 Line Voltage Sensing
        2. 3.3.4.2 Arc Gap Voltage Sensing
        3. 3.3.4.3 Differential to Single-Ended Conversion
      5. 3.3.5 Power Supply
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software
    3. 4.3 Test Setup
      1. 4.3.1 Arc Testing Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

MSPM0G5187-LP

MSPM0G5187 microcontrollers (MCUs) belong to the MSP highly integrated, ultra-low-power 32-bit MCU family. The enhanced Arm® Cortex® ®-M0+ 32-bit core platform forms the base for these MCUs. The platform operates at frequencies up to 80MHz. These MCUs blend cost optimization and design flexibility. Applications require 32KB to 128KB flash memory. Small packages measure down to 4mm × 4mm. High pin count packages offer up to 64 pins.

These devices include an Edge AI NPU accelerator, cybersecurity enablers, and high performance integrated analog. The devices deliver excellent low-power performance across the operating temperature range. Up to 128KB embedded flash program memory includes built-in error correction code (ECC). Up to 32KB SRAM includes ECC and parity protection.

Flash memory organizes into two main banks to support field firmware updates. Address swap support operates between the two main banks. TI's Edge AI NPU functions as an integrated accelerator module. The module enhances fast, secure AI at the edge with sensing, processing, and control applications within the MSPM0 platform.

Flexible cybersecurity enablers support secure boot, secure in-field firmware updates, IP protection (execute-only memory), and key storage. Hardware acceleration operates for various AES symmetric cipher modes. The cybersecurity architecture awaits Arm PSA Level 1 certification.

High-performance analog modules include one sampling 12-bit 1.6Msps ADC supporting up to 26 external channels. On-chip voltage reference operates at 1.4V or 2.5V. One high-speed comparator includes built-in 8-bit reference DAC.