SNAS800A July   2021  – August 2022 LMX1204

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Temperature Sensor
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Clock Output Buffers
        2. 7.3.3.2 Clock MUX
        3. 7.3.3.3 Clock Divider
        4. 7.3.3.4 Clock Multiplier and Filter Modes
          1. 7.3.3.4.1 State Machine Clock
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      5. 7.3.5 SYSREF
        1. 7.3.5.1 SYSREF Output Buffers
          1. 7.3.5.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 7.3.5.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.5.2 SYSREF Frequency and Delay Generation
        3. 7.3.5.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 7.3.5.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 7.3.5.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.5.4 SYNC Feature
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 300-MHz to 12.8-GHz output frequency
  • Ultra-low noise
    • Noise floor of –161 dBc/Hz at 6-GHz output
    • 1/f Noise of –154 dBc/Hz at 6-GHz output, 10-kHz offset
    • Under 30-fs additive jitter (DC to fCLK integration range)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divider that supports ÷1 (buffer mode), ÷2,3,4,5,6,7, and 8
    • Shared PLL-based multiplier that supports x1 (filter mode), x2, x3, and x4
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • ÷1, 2, 4 pre-divider
    • ÷1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5 ps each at 12.8 GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5-V operating voltage
  • –40ºC to +85ºC operating temperature