Packaging information
| Package | Pins TSSOP (DGG) | 48 |
| Operating temperature range (°C) -10 to 70 |
| Package qty | Carrier 38 | TUBE |
Features for the DS90CR217
- 20 to 85 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best-in-Class Set & Hold Times on TxINPUTs
- Low Power Consumption
- ±1V Common-Mode Range (Around +1.2V)
- Narrow Bus Reduces Cable Size and Cost
- Up to 1.785 Gbps Throughput
- Up to 223 Mbytes/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires No External Components
- Rising Edge Data Strobe
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 48-Lead TSSOP Package
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Description for the DS90CR217
The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 1.785 Gbit/s (223 Mbytes/sec).
The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.