Product details

2nd harmonic (dBc) -73 3rd harmonic (dBc) -80 @ MHz 200 Acl, min spec gain (V/V) 0.5 Architecture VGA, Fully Differential ADC Driver BW @ Acl (MHz) 4500 Gain (Max) (dB) 26 Gain (Min) (dB) -6 Step size (dB) 1 Type RF VGA Iq per channel (Typ) (mA) 69 Number of channels (#) 1 Rating Catalog Operating temperature range (C) -40 to 85 Slew rate (Typ) (V/us) 18200 Total supply voltage (Max) (+5V=5, +/-5V=10) 5.25 Total supply voltage (Min) (+5V=5, +/-5V=10) 4 Vs (Min) (V) 4 Vs (Max) (V) 5
2nd harmonic (dBc) -73 3rd harmonic (dBc) -80 @ MHz 200 Acl, min spec gain (V/V) 0.5 Architecture VGA, Fully Differential ADC Driver BW @ Acl (MHz) 4500 Gain (Max) (dB) 26 Gain (Min) (dB) -6 Step size (dB) 1 Type RF VGA Iq per channel (Typ) (mA) 69 Number of channels (#) 1 Rating Catalog Operating temperature range (C) -40 to 85 Slew rate (Typ) (V/us) 18200 Total supply voltage (Max) (+5V=5, +/-5V=10) 5.25 Total supply voltage (Min) (+5V=5, +/-5V=10) 4 Vs (Min) (V) 4 Vs (Max) (V) 5
UQFN-HR (RMZ) 16 9 mm² 3 x 3
  • 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
  • Gain Range: –6 dB to 26 dB in 1-dB Steps
  • Differential Input Impedance: 100 Ω
  • Differential Output with Common-Mode Control
  • Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
    • 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
    • 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
    • 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
    • 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
  • Output IP3:
    • 43 dBm at 200 MHz
    • 33 dBm at 1 GHz
    • 27 dBm at 2 GHz
  • Output IP2:
    • 67 dBm at 200 MHz
    • 60 dBm at 1 GHz
    • 52 dBm at 2 GHz
  • 8-dB Noise Figure at 1 GHz, RS = 100 Ω
  • 82-ps Rise, Fall Time Pulse Response
  • Supply Operation: 5.0 V at 69 mA
  • Supports Single- and (±) Split-Supply Operation:
    • DC- and AC-Coupled Applications
  • Fabricated on an Advanced Complementary BiCMOS Process
  • 3-mm × 3-mm UQFN-16 Package
  • 3-dB Bandwidth: 4.5 GHz at 26-dB Gain
  • Gain Range: –6 dB to 26 dB in 1-dB Steps
  • Differential Input Impedance: 100 Ω
  • Differential Output with Common-Mode Control
  • Distortion at Max Gain (VO = 2 VPPD, RL = 200 Ω):
    • 200 MHz: HD2 at –73 dBc, HD3 at –80 dBc
    • 500 MHz: HD2 at –68 dBc, HD3 at –72 dBc
    • 1 GHz: HD2 at –63 dBc, HD3 at –63 dBc
    • 2 GHz: HD2 at –58 dBc, HD3 at –54 dBc
  • Output IP3:
    • 43 dBm at 200 MHz
    • 33 dBm at 1 GHz
    • 27 dBm at 2 GHz
  • Output IP2:
    • 67 dBm at 200 MHz
    • 60 dBm at 1 GHz
    • 52 dBm at 2 GHz
  • 8-dB Noise Figure at 1 GHz, RS = 100 Ω
  • 82-ps Rise, Fall Time Pulse Response
  • Supply Operation: 5.0 V at 69 mA
  • Supports Single- and (±) Split-Supply Operation:
    • DC- and AC-Coupled Applications
  • Fabricated on an Advanced Complementary BiCMOS Process
  • 3-mm × 3-mm UQFN-16 Package

The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).

Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.

Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.

This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.

The LMH6401 is a wideband, digitally-controlled, variable-gain amplifier (DVGA) designed for dc to radio frequency (RF), intermediate frequency (IF), and high-speed time-domain applications. The device is an ideal analog-to-digital converter (ADC) driver for dc- or ac-coupled applications that require an automatic gain control (AGC).

Noise and distortion performance is optimized to drive ultra-wideband ADCs. The amplifier has an 8-dB noise figure at maximum gain and a –63-dBc harmonic distortion at 1 GHz for full-scale signal levels. The device supports both single- and split-supply operation for driving an ADC. A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input requirements.

Gain control is performed via an SPI™ interface, allowing a 32-dB gain range from –6 dB to 26 dB in 1-dB steps. A power-down feature is also available through the external PD pin or SPI control.

This level of performance is achieved at a low power level of 345 mW. The operating ambient temperature range is –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier datasheet (Rev. A) PDF | HTML 19 May 2015
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 Mar 2017
Application note ADC32RF45: Amplifier to ADC Interface (Rev. A) 07 Sep 2016
Technical article Disentangle RF amplifier specs: output voltage/current and 1dB compression point 09 Jun 2016
Technical article Disentangle RF amplifier specs: intermodulation distortion and intercept points 19 Apr 2016
Technical article Disentangling RF amplifier specs: amplifier spot noise vs. noise figure 05 Feb 2016
EVM User's guide TSW54J60 Evaluation Module User's Guide (Rev. A) 21 Sep 2015
EVM User's guide LMH6401 EVM User's Guide (Rev. A) 29 May 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMH6401EVM — LMH6401 evaluation module

The LMH6401 Evaluation module (EVM) is used to evaluate the single LMH6401, digitally-controlled variable-gain amplifier (DVGA) in a 16-lead high-performance RF package.  The EVM is designed to quickly and easily demonstrate the functionality and performance of LMH6401 across all the gain (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

LMH6401EVM GUI (Rev. B)

SBOC451B.ZIP (204171 KB)
lock = Requires export approval (1 minute)
Simulation model

LMH6401 TINA-TI Spice Model

SBOM938.ZIP (14 KB) - TINA-TI Spice Model
Simulation model

LMH6401 TINA-TI Reference Design (Rev. A)

SBOM939A.TSC (58 KB) - TINA-TI Reference Design
Simulation model

LMH6401 PSpice Model

SBOMBQ6.ZIP (67 KB) - PSpice Model
Simulation model

LMH6401 IBIS MODEL

SNOM552.ZIP (21 KB) - IBIS Model
Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Schematic: PDF
Reference designs

TIDA-010122 — Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems

This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local (...)
Schematic: PDF
Reference designs

TIDA-010128 — Scalable 20.8 GSPS reference design for 12 bit digitizers

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Schematic: PDF
Reference designs

TIDA-01028 — 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Schematic: PDF
Reference designs

TIDA-00823 — 16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Fixed Gain Amplifier

This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Schematic: PDF
Reference designs

TIDA-00826 — 50-Ohm 2-GHz Oscilloscope Front-end Reference Design

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Schematic: PDF
Reference designs

TIDA-00822 — 16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Variable Gain Amplifier

This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Schematic: PDF
Reference designs

TIDA-00654 — Cascaded LMH5401 and LMH6401 reference design

A wideband single-ended to differential conversion reference design in both DC- and AC- coupled applications is presented. The design evaluates the performance of the LMH5401 and LMH6401 cascade and offers insight into the design.
Schematic: PDF
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UQFN-HR (RMZ) 16 View options

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