Home Logic & voltage translation Buffers, drivers & transceiver Inverting buffers & drivers
Home
Logic & voltage translation
Buffers, drivers & transceiver
Inverting buffers & drivers

SN74AUP1G14

ACTIVE

Single 0.8-V to 3.6-V low power inverter with Schmitt-Trigger inputs

Order now
Data sheet

SN74AUP1G14

ACTIVE
Data sheet Order now

Product details

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 4 1 mm² 1 x 1 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.9 ns Maximum at 3.3 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.9 ns Maximum at 3.3 V

The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable applications. This family assures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see AUP – The Lowest-Power Family and Excellent Signal Integrity).

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
filter Find other Inverting buffers & drivers
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
SN74AHC1G14 ACTIVE Single 2-V to 5.5-V inverter with Schmitt-Trigger inputs Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA
SN74LVC1G08-Q1 ACTIVE Automotive, 1-ch, 2-input 1.65-V to 5.5-V 32-mA drive strength AND gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G10 ACTIVE Single 3-input, 1.65-V to 5.5-V NAND gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G11 ACTIVE 1-ch, 3-input 1.65-V to 5.5-V 32 mA drive strength AND gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G14 ACTIVE Single 1.65-V to 5.5-V inverter with Schmitt-Trigger inputs Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G14-Q1 ACTIVE Automotive single 1.65-V to 5.5-V inverter with Schmitt-Trigger inputs Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G27 ACTIVE Single 3-input, 1.65-V to 5.5-V NOR gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G32-Q1 ACTIVE Automotive, 1-ch, 2-input 1.65-V to 5.5-V 32-mA drive strength OR gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G332 ACTIVE 1-ch, 3-input 1.65-V to 5.5-V 32-mA drive strength OR gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
SN74LVC1G386 ACTIVE Single 3-input, 1.65-V to 5.5-V XOR (exclusive OR) gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA
Similar functionality to the compared device
SN74LVC3G98 ACTIVE Three-channel configurable multiple-function gate Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 8
Top documentation Type Title Format options Date
* Data sheet SN74AUP1G14 Low-Power Single Schmitt-Trigger Inverter datasheet (Rev. J) PDF | HTML 02 Nov 2017
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 17 Apr 2025
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) 01 May 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

User guide: PDF | HTML
Not available on TI.com
Simulation model

HSPICE Model of SN74AUP1G14

SCEJ166.ZIP (87 KB) - HSpice Model
Download
Simulation model

SN74AUP1G14 Behavioral SPICE Model

SCEM687.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74AUP1G14 IBIS Model (Rev. A)

SCEM424A.ZIP (64 KB) - IBIS Model
Download
Reference designs

TIDA-00377 — Self-Powered AC Solid State Relay with MOSFETs Reference Design

The self-powered AC solid state relay with MOSFETs reference design is a single relay replacement that enables efficient power management for a low-power alternative to standard electromechanical relays in thermostat applications. This SSR reference design is self-powered through the 24V AC power (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
DSBGA (YFP) 4 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos